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yosys/techlibs/ice40
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Clifford Wolf 516e8828f2 Don't write a 17th memory bit in ice40/cells_sim (by Larry Doolittle) 2015-07-27 22:44:01 +02:00
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tests Initialization support for all iCE40 bram modes 2015-04-26 08:39:31 +02:00
.gitignore Initialization support for all iCE40 bram modes 2015-04-26 08:39:31 +02:00
Makefile.inc Verific build fixes 2015-05-17 08:19:52 +02:00
arith_map.v Fixed trailing whitespaces 2015-07-02 11:14:30 +02:00
brams.txt iCE40: set min bram efficiency to 2% 2015-06-20 09:31:19 +02:00
brams_init.py Initialization support for all iCE40 bram modes 2015-04-26 08:39:31 +02:00
brams_map.v Initialization support for all iCE40 bram modes 2015-04-26 08:39:31 +02:00
cells_map.v improved ice40 dff cell mapping 2015-04-16 11:30:56 +02:00
cells_sim.v Don't write a 17th memory bit in ice40/cells_sim (by Larry Doolittle) 2015-07-27 22:44:01 +02:00
ice40_ffssr.cc Fixed trailing whitespaces 2015-07-02 11:14:30 +02:00
ice40_opt.cc Fixed trailing whitespaces 2015-07-02 11:14:30 +02:00
synth_ice40.cc Fixed trailing whitespaces 2015-07-02 11:14:30 +02:00