yosys/passes
Jannis Harder ad2b04d63a sim: Fix cosimulation with nested modules having unconnected inputs
When assigning values to input ports of nested modules in cosimulation,
sim needs to find the actual driver of the signal to perform the
assignment. The existing code didn't handle unconnected inputs in that
scenario.
2023-05-18 16:50:11 +02:00
..
cmds Merge pull request #3749 from lethalbit/aki/plugin-stuff 2023-05-09 08:46:02 +02:00
equiv Merge pull request #3126 from georgerennie/equiv_make_assertions 2023-02-14 17:15:55 +01:00
fsm add option to fsm_detect to ignore self-resetting 2023-01-30 16:12:53 +01:00
hierarchy Small bugfix in uniquify pass 2022-12-21 10:41:48 +01:00
memory Fitting help messages to 80 character width 2022-08-24 10:40:57 +12:00
opt Fixes for some of clang scan-build detected issues 2023-01-17 12:58:08 +01:00
pmgen Fitting help messages to 80 character width 2022-08-24 10:40:57 +12:00
proc Fixes for some of clang scan-build detected issues 2023-01-17 12:58:08 +01:00
sat sim: Fix cosimulation with nested modules having unconnected inputs 2023-05-18 16:50:11 +02:00
techmap Merge branch 'YosysHQ:master' into main/issue2525 2023-05-16 21:21:32 -07:00
tests Add $bmux and $demux cells. 2022-01-28 23:34:41 +01:00