Clifford Wolf fecd3aa2b1 Merge pull request #1147 from YosysHQ/clifford/fix1144 ... Improve specify dummy parser		2019-07-09 18:47:08 +01:00
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.gitignore	Add "make coverage"	2018-08-27 14:22:21 +02:00
Makefile.inc	Read bigger Verilog files.	2019-05-18 14:20:30 +03:00
const2ast.cc	Fix segfault on failed VERILOG_FRONTEND::const2ast, closes #1131	2019-06-26 11:09:43 +02:00
preproc.cc	Support SystemVerilog `` extension for macros	2018-05-17 00:09:56 -04:00
verilog_frontend.cc	Add "read_verilog -pwires" feature, closes #1106	2019-06-19 14:38:50 +02:00
verilog_frontend.h	Add specify parser	2019-04-23 21:36:59 +02:00
verilog_lexer.l	Fix read_verilog assert/assume/etc on default case label, fixes YosysHQ/SymbiYosys#53	2019-07-09 18:46:28 +01:00
verilog_parser.y	Merge pull request #1147 from YosysHQ/clifford/fix1144	2019-07-09 18:47:08 +01:00