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tests
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ecp5: Add simulation equivalence check for Diamond FF implementations
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2019-08-30 13:27:36 +01:00 |
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.gitignore
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ecp5: Add support for mapping 36-bit wide PDP BRAMs
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2019-10-01 13:46:36 +01:00 |
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Makefile.inc
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ecp5: cleanup unused +/ecp5/abc9_model.v
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2020-05-23 08:17:40 -07:00 |
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arith_map.v
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Add force_downto and force_upto wire attributes.
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2020-05-19 01:42:40 +02:00 |
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brams.txt
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ecp5: add support for both 1364.1 and LSE RAM/ROM attributes.
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2020-02-06 16:52:51 +00:00 |
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brams_connect.py
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ecp5: Add support for mapping 36-bit wide PDP BRAMs
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2019-10-01 13:46:36 +01:00 |
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brams_init.py
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ecp5: First BRAM type maps successfully
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2018-10-10 16:35:19 +01:00 |
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brams_map.v
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remove unused parameters
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2020-03-06 16:45:36 +01:00 |
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cells_bb.v
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ecp5: Add missing SERDES parameters
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2020-05-12 21:12:26 +01:00 |
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cells_ff.vh
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Fix bitwidth mismatch; suppresses iverilog warning
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2019-12-11 13:02:07 -08:00 |
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cells_io.vh
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ecp5: deduplicate Diamond FD/IFS/OFS/IO primitives.
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2019-08-30 10:05:09 +00:00 |
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cells_map.v
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Add force_downto and force_upto wire attributes.
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2020-05-19 01:42:40 +02:00 |
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cells_sim.v
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ecp5: TRELLIS_FF bypass path only in async mode
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2020-05-14 10:33:56 -07:00 |
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dsp_map.v
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ecp5: Force SIGNED ports to be 1 bit
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2020-04-16 16:38:19 +01:00 |
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ecp5_ffinit.cc
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Cleanup use of hard-coded default parameters in light of #1945
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2020-04-22 12:02:30 -07:00 |
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ecp5_gsr.cc
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ecp5: ecp5_gsr to skip cells that don't have GSR parameter again
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2020-04-22 17:53:08 -07:00 |
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latches_map.v
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ecp5: Add latch inference
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2018-10-19 15:16:40 +01:00 |
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lutrams.txt
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ecp5: add support for both 1364.1 and LSE RAM/ROM attributes.
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2020-02-06 16:52:51 +00:00 |
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lutrams_map.v
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synth_ecp5: rename dram to lutram everywhere.
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2019-07-16 20:45:12 +00:00 |
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synth_ecp5.cc
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ecp5: cleanup unused +/ecp5/abc9_model.v
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2020-05-23 08:17:40 -07:00 |
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