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yosys/passes/opt
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Clifford Wolf 8927aa6148 Removed $bu0 cell type 2014-09-04 02:07:52 +02:00
..
Makefile.inc Moved "share" and "wreduce" to passes/opt/ 2014-09-01 11:45:26 +02:00
opt.cc Added design->scratchpad 2014-08-30 19:37:12 +02:00
opt_clean.cc Added design->scratchpad 2014-08-30 19:37:12 +02:00
opt_const.cc Removed $bu0 cell type 2014-09-04 02:07:52 +02:00
opt_muxtree.cc Added design->scratchpad 2014-08-30 19:37:12 +02:00
opt_reduce.cc Added design->scratchpad 2014-08-30 19:37:12 +02:00
opt_rmdff.cc Added design->scratchpad 2014-08-30 19:37:12 +02:00
opt_share.cc Using std::vector<RTLIL::State> instead of RTLIL::Const for RTLIL::SigChunk::data 2014-09-01 11:36:02 +02:00
share.cc Removed $bu0 cell type 2014-09-04 02:07:52 +02:00
wreduce.cc Removed $bu0 cell type 2014-09-04 02:07:52 +02:00