yosys/passes/proc
Clifford Wolf 1c85584fe5 Do not create $dffsr cells with no-op resets in proc_dff 2014-06-19 12:29:29 +02:00
..
Makefile.inc Major improvements in mem2reg and added "init" sync rules 2013-11-21 13:49:00 +01:00
proc.cc Major improvements in mem2reg and added "init" sync rules 2013-11-21 13:49:00 +01:00
proc_arst.cc Added workaround for vhdl-style edge triggers from vhdl2verilog to proc_arst 2014-02-21 23:34:45 +01:00
proc_clean.cc Added handling of multiple async paths in proc_arst 2013-10-19 00:50:13 +02:00
proc_dff.cc Do not create $dffsr cells with no-op resets in proc_dff 2014-06-19 12:29:29 +02:00
proc_init.cc Major improvements in mem2reg and added "init" sync rules 2013-11-21 13:49:00 +01:00
proc_mux.cc Tiny cleanup in proc_mux.cc 2014-01-03 16:54:59 +01:00
proc_rmdead.cc Added help messages to proc_* passes 2013-03-01 09:26:29 +01:00