Graham Edgecombe f93e6637aa Fix port names in SB_IO_OD		2017-12-10 15:33:38 +00:00
..
tests	Initialization support for all iCE40 bram modes	2015-04-26 08:39:31 +02:00
.gitignore	Initialization support for all iCE40 bram modes	2015-04-26 08:39:31 +02:00
Makefile.inc	Added synth_ice40 support for latches via logic loops	2016-05-06 23:02:37 +02:00
arith_map.v	Fixed trailing whitespaces	2015-07-02 11:14:30 +02:00
brams.txt	Added read-enable to memory model	2015-09-25 12:23:11 +02:00
brams_init.py	Switched to Python 3	2015-08-22 09:59:33 +02:00
brams_map.v	Fixed WE/RE usage in iCE40 BRAM mapping	2015-11-24 10:51:34 +01:00
cells_map.v	Add "synth_ice40 -vpr"	2017-11-16 21:37:02 +01:00
cells_sim.v	Fix port names in SB_IO_OD	2017-12-10 15:33:38 +00:00
ice40_ffinit.cc	Minor fixes in ice40_ff* passes for sloppy SB_DFF instantiations	2016-07-08 14:41:36 +02:00
ice40_ffssr.cc	Minor fixes in ice40_ff* passes for sloppy SB_DFF instantiations	2016-07-08 14:41:36 +02:00
ice40_opt.cc	Fixed ice40_opt lut unmapping, added "ice40_opt -unlut"	2016-05-06 14:32:32 +02:00
latches_map.v	Added synth_ice40 support for latches via logic loops	2016-05-06 23:02:37 +02:00
synth_ice40.cc	Fix spelling in -vpr help for synth_ice40	2017-12-08 18:44:45 -08:00