yosys/passes
Clifford Wolf 88182e46d7 Check for memories in clk2fflogic 2017-12-13 19:14:34 +01:00
..
cmds Add support for editline as replacement for readline 2017-11-08 02:55:00 +01:00
equiv Fix equiv_simple, old behavior now available with "equiv_simple -short" 2017-04-28 18:57:53 +02:00
fsm Remove some dead code from fsm_map 2017-08-21 15:02:16 +02:00
hierarchy Rename "singleton" pass to "uniquify" 2017-08-20 12:31:50 +02:00
memory Typo fix. 2016-09-08 10:57:16 +03:00
opt Add warnings for driver-driver conflicts between FFs (and other cells) and constants 2017-12-12 17:13:27 +01:00
proc Add warnings for driver-driver conflicts between FFs (and other cells) and constants 2017-12-12 17:13:27 +01:00
sat Check for memories in clk2fflogic 2017-12-13 19:14:34 +01:00
techmap Rewrite ABC output to include proper net names in timing report 2017-10-10 13:32:58 +02:00
tests Add $live and $fair cell types, add support for s_eventually keyword 2017-02-25 10:36:39 +01:00