mirror of https://github.com/YosysHQ/yosys.git
430 lines
12 KiB
Plaintext
430 lines
12 KiB
Plaintext
// This file describes the main pattern matcher setup (of three total) that
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// forms the `xilinx_dsp` pass described in xilinx_dsp.cc - version for
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// DSP48A/DSP48A1 (Spartan 3A DSP, Spartan 6).
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// At a high level, it works as follows:
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// ( 1) Starting from a DSP48A/DSP48A1 cell
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// ( 2) Match the driver of the 'B' input to a possible $dff cell (B1REG)
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// If B1REG matched, treat 'B' input as input of B1REG
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// ( 3) Match the driver of the 'B' and 'D' inputs for a possible $add cell
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// (pre-adder)
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// ( 4) Match 'B' input for B0REG
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// ( 5) Match 'A' input for A1REG
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// If A1REG, then match 'A' input for A0REG
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// ( 6) Match 'D' input for DREG
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// ( 7) Match 'P' output that exclusively drives an MREG
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// ( 8) Match 'P' output that exclusively drives one of two inputs to an $add
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// cell (post-adder).
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// The other input to the adder is assumed to come in from the 'C' input
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// (note: 'P' -> 'C' connections that exist for accumulators are
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// recognised in xilinx_dsp.cc).
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// ( 9) Match 'P' output that exclusively drives a PREG
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// (10) If post-adder and PREG both present, match for a $mux cell driving
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// the 'C' input, where one of the $mux's inputs is the PREG output.
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// This indicates an accumulator situation, and one where a $mux exists
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// to override the accumulated value:
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// +--------------------------------+
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// | ____ |
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// +--| \ |
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// |$mux|-+ |
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// 'C' ---|____/ | |
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// | /-------\ +----+ |
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// +----+ +-| post- |___|PREG|---+ 'P'
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// |MREG|------ | adder | +----+
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// +----+ \-------/
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// Notes: see the notes in xilinx_dsp.pmg
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pattern xilinx_dsp48a_pack
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state <SigBit> clock
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state <SigSpec> sigA sigB sigC sigD sigM sigP
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state <IdString> postAddAB postAddMuxAB
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state <Cell*> ffA0 ffA1
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state <Cell*> ffB0 ffB1
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state <Cell*> ffD ffM ffP
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// Variables used for subpatterns
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state <SigSpec> argQ argD
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udata <SigSpec> dffD dffQ
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udata <SigBit> dffclock
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udata <Cell*> dff
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// (1) Starting from a DSP48A/DSP48A1 cell
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match dsp
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select dsp->type.in(\DSP48A, \DSP48A1)
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endmatch
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code sigA sigB sigC sigD sigM clock
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auto unextend = [](const SigSpec &sig) {
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int i;
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for (i = GetSize(sig)-1; i > 0; i--)
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if (sig[i] != sig[i-1])
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break;
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// Do not remove non-const sign bit
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if (sig[i].wire)
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++i;
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return sig.extract(0, i);
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};
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sigA = unextend(port(dsp, \A));
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sigB = unextend(port(dsp, \B));
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sigC = port(dsp, \C, SigSpec());
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sigD = port(dsp, \D, SigSpec());
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SigSpec P = port(dsp, \P);
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// Only care about those bits that are used
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int i;
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for (i = GetSize(P)-1; i >= 0; i--)
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if (nusers(P[i]) > 1)
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break;
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i++;
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log_assert(nusers(P.extract_end(i)) <= 1);
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// This sigM could have no users if downstream sinks (e.g. $add) is
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// narrower than $mul result, for example
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if (i == 0)
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reject;
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sigM = P.extract(0, i);
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clock = port(dsp, \CLK, SigBit());
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endcode
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// (2) Match the driver of the 'B' input to a possible $dff cell (B1REG)
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// (attached to at most two $mux cells that implement clock-enable or
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// reset functionality, using a subpattern discussed above)
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// If matched, treat 'B' input as input of B1REG
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code argQ ffB1 sigB clock
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if (param(dsp, \B1REG).as_int() == 0 && param(dsp, \B0REG).as_int() == 0 && port(dsp, \OPMODE, SigSpec()).extract(4, 1).is_fully_zero()) {
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argQ = sigB;
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subpattern(in_dffe);
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if (dff) {
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ffB1 = dff;
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clock = dffclock;
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sigB = dffD;
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}
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}
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endcode
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// (3) Match the driver of the 'B' and 'D' inputs for a possible $add cell
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// (pre-adder)
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match preAdd
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if sigD.empty() || sigD.is_fully_zero()
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if param(dsp, \B0REG).as_int() == 0
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// Ensure that preAdder not already used
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if port(dsp, \OPMODE, SigSpec()).extract(4, 1).is_fully_zero()
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select preAdd->type.in($add, $sub)
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// Output has to be 18 bits or less
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select GetSize(port(preAdd, \Y)) <= 18
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select nusers(port(preAdd, \Y)) == 2
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// D port has to be 18 bits or less
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select GetSize(port(preAdd, \A)) <= 18
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// B port has to be 18 bits or less
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select GetSize(port(preAdd, \B)) <= 18
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index <SigSpec> port(preAdd, \Y) === sigB
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optional
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endmatch
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code sigB sigD
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if (preAdd) {
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sigD = port(preAdd, \A);
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sigB = port(preAdd, \B);
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}
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endcode
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// (4) Match 'B' input for B0REG
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code argQ ffB0 sigB clock
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if (param(dsp, \B0REG).as_int() == 0) {
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argQ = sigB;
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subpattern(in_dffe);
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if (dff) {
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if (ffB1) {
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if (dff->type != ffB1->type)
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goto ffB0_end;
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if (dff->type.in($sdff, $sdffe, $sdffce)) {
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if (param(dff, \SRST_POLARITY) != param(ffB1, \SRST_POLARITY))
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goto ffB0_end;
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if (port(dff, \SRST) != port(ffB1, \SRST))
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goto ffB0_end;
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}
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if (dff->type.in($dffe, $sdffe, $sdffce)) {
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if (param(dff, \EN_POLARITY) != param(ffB1, \EN_POLARITY))
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goto ffB0_end;
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if (port(dff, \EN) != port(ffB1, \EN))
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goto ffB0_end;
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}
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}
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ffB0 = dff;
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clock = dffclock;
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sigB = dffD;
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}
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}
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ffB0_end:
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endcode
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// (5) Match 'A' input for A1REG
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// If A1REG, then match 'A' input for A0REG
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code argQ ffA1 sigA clock ffA0
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if (param(dsp, \A0REG).as_int() == 0 && param(dsp, \A1REG).as_int() == 0) {
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argQ = sigA;
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subpattern(in_dffe);
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if (dff) {
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ffA1 = dff;
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clock = dffclock;
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sigA = dffD;
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// Now attempt to match A0
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if (ffA1) {
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argQ = sigA;
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subpattern(in_dffe);
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if (dff) {
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if (dff->type != ffA1->type)
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goto ffA0_end;
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if (dff->type.in($sdff, $sdffe, $sdffce)) {
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if (param(dff, \SRST_POLARITY) != param(ffA1, \SRST_POLARITY))
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goto ffA0_end;
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if (port(dff, \SRST) != port(ffA1, \SRST))
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goto ffA0_end;
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}
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if (dff->type.in($dffe, $sdffe, $sdffce)) {
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if (param(dff, \EN_POLARITY) != param(ffA1, \EN_POLARITY))
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goto ffA0_end;
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if (port(dff, \EN) != port(ffA1, \EN))
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goto ffA0_end;
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}
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ffA0 = dff;
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clock = dffclock;
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sigA = dffD;
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ffA0_end: ;
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}
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}
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}
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}
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endcode
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// (6) Match 'D' input for DREG
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code argQ ffD sigD clock
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if (param(dsp, \DREG).as_int() == 0) {
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argQ = sigD;
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subpattern(in_dffe);
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if (dff) {
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ffD = dff;
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clock = dffclock;
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sigD = dffD;
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}
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}
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endcode
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// (7) Match 'P' output that exclusively drives an MREG
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code argD ffM sigM sigP clock
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if (param(dsp, \MREG).as_int() == 0 && nusers(sigM) == 2) {
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argD = sigM;
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subpattern(out_dffe);
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if (dff) {
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ffM = dff;
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clock = dffclock;
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sigM = dffQ;
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}
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}
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sigP = sigM;
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endcode
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// (8) Match 'P' output that exclusively drives one of two inputs to an $add
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// cell (post-adder).
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// The other input to the adder is assumed to come in from the 'C' input
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// (note: 'P' -> 'C' connections that exist for accumulators are
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// recognised in xilinx_dsp.cc).
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match postAdd
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// Ensure that Z mux is not already used
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if port(dsp, \OPMODE, SigSpec()).extract(2,2).is_fully_zero()
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select postAdd->type.in($add)
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select GetSize(port(postAdd, \Y)) <= 48
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choice <IdString> AB {\A, \B}
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select nusers(port(postAdd, AB)) == 2
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index <SigBit> port(postAdd, AB)[0] === sigP[0]
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filter GetSize(port(postAdd, AB)) >= GetSize(sigP)
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filter port(postAdd, AB).extract(0, GetSize(sigP)) == sigP
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// Check that remainder of AB is a sign- or zero-extension
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filter port(postAdd, AB).extract_end(GetSize(sigP)) == SigSpec(sigP[GetSize(sigP)-1], GetSize(port(postAdd, AB))-GetSize(sigP)) || port(postAdd, AB).extract_end(GetSize(sigP)) == SigSpec(State::S0, GetSize(port(postAdd, AB))-GetSize(sigP))
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set postAddAB AB
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optional
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endmatch
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code sigC sigP
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if (postAdd) {
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sigC = port(postAdd, postAddAB == \A ? \B : \A);
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sigP = port(postAdd, \Y);
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}
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endcode
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// (9) Match 'P' output that exclusively drives a PREG
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code argD ffP sigP clock
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if (param(dsp, \PREG).as_int() == 0) {
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if (nusers(sigP) == 2) {
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argD = sigP;
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subpattern(out_dffe);
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if (dff) {
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ffP = dff;
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clock = dffclock;
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sigP = dffQ;
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}
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}
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}
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endcode
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// (10) If post-adder and PREG both present, match for a $mux cell driving
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// the 'C' input, where one of the $mux's inputs is the PREG output.
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// This indicates an accumulator situation, and one where a $mux exists
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// to override the accumulated value:
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// +--------------------------------+
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// | ____ |
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// +--| \ |
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// |$mux|-+ |
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// 'C' ---|____/ | |
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// | /-------\ +----+ |
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// +----+ +-| post- |___|PREG|---+ 'P'
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// |MREG|------ | adder | +----+
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// +----+ \-------/
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match postAddMux
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if postAdd
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if ffP
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select postAddMux->type.in($mux)
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select nusers(port(postAddMux, \Y)) == 2
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choice <IdString> AB {\A, \B}
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index <SigSpec> port(postAddMux, AB) === sigP
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index <SigSpec> port(postAddMux, \Y) === sigC
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set postAddMuxAB AB
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optional
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endmatch
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code sigC
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if (postAddMux)
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sigC = port(postAddMux, postAddMuxAB == \A ? \B : \A);
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endcode
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code
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accept;
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endcode
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// #######################
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// Subpattern for matching against input registers, based on knowledge of the
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// 'Q' input.
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subpattern in_dffe
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arg argQ clock
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code
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dff = nullptr;
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if (argQ.empty())
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reject;
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for (const auto &c : argQ.chunks()) {
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// Abandon matches when 'Q' is a constant
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if (!c.wire)
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reject;
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// Abandon matches when 'Q' has the keep attribute set
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if (c.wire->get_bool_attribute(\keep))
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reject;
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// Abandon matches when 'Q' has a non-zero init attribute set
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// (not supported by DSP48E1)
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Const init = c.wire->attributes.at(\init, Const());
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if (!init.empty())
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for (auto b : init.extract(c.offset, c.width))
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if (b != State::Sx && b != State::S0)
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reject;
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}
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endcode
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match ff
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select ff->type.in($dff, $dffe, $sdff, $sdffe)
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// DSP48E1 does not support clock inversion
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select param(ff, \CLK_POLARITY).as_bool()
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// Check that reset value, if present, is fully 0.
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filter ff->type.in($dff, $dffe) || param(ff, \SRST_VALUE).is_fully_zero()
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slice offset GetSize(port(ff, \D))
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index <SigBit> port(ff, \Q)[offset] === argQ[0]
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// Check that the rest of argQ is present
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filter GetSize(port(ff, \Q)) >= offset + GetSize(argQ)
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filter port(ff, \Q).extract(offset, GetSize(argQ)) == argQ
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filter clock == SigBit() || port(ff, \CLK)[0] == clock
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endmatch
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code argQ
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SigSpec Q = port(ff, \Q);
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dff = ff;
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dffclock = port(ff, \CLK);
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dffD = argQ;
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SigSpec D = port(ff, \D);
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argQ = Q;
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dffD.replace(argQ, D);
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endcode
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// #######################
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// Subpattern for matching against output registers, based on knowledge of the
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// 'D' input.
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// At a high level:
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// (1) Starting from an optional $mux cell that implements clock enable
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// semantics --- one where the given 'D' argument (partially or fully)
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// drives one of its two inputs
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// (2) Starting from, or continuing onto, another optional $mux cell that
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// implements synchronous reset semantics --- one where the given 'D'
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// argument (or the clock enable $mux output) drives one of its two inputs
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// and where the other input is fully zero
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// (3) Match for a $dff cell (whose 'D' input is the 'D' argument, or the
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// output of the previous clock enable or reset $mux cells)
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subpattern out_dffe
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arg argD argQ clock
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code
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dff = nullptr;
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for (auto c : argD.chunks())
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// Abandon matches when 'D' has the keep attribute set
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if (c.wire->get_bool_attribute(\keep))
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reject;
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endcode
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match ff
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select ff->type.in($dff, $dffe, $sdff, $sdffe)
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// DSP48E1 does not support clock inversion
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select param(ff, \CLK_POLARITY).as_bool()
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slice offset GetSize(port(ff, \D))
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index <SigBit> port(ff, \D)[offset] === argD[0]
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// Check that the rest of argD is present
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filter GetSize(port(ff, \D)) >= offset + GetSize(argD)
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filter port(ff, \D).extract(offset, GetSize(argD)) == argD
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filter clock == SigBit() || port(ff, \CLK)[0] == clock
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endmatch
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code argQ
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SigSpec D = port(ff, \D);
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SigSpec Q = port(ff, \Q);
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argQ = argD;
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argQ.replace(D, Q);
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// Abandon matches when 'Q' has a non-zero init attribute set
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// (not supported by DSP48E1)
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for (auto c : argQ.chunks()) {
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Const init = c.wire->attributes.at(\init, Const());
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if (!init.empty())
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for (auto b : init.extract(c.offset, c.width))
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if (b != State::Sx && b != State::S0)
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reject;
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}
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dff = ff;
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dffQ = argQ;
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dffclock = port(ff, \CLK);
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endcode
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