mirror of https://github.com/YosysHQ/yosys.git
440 lines
12 KiB
Plaintext
440 lines
12 KiB
Plaintext
// ISC License
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//
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// Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
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//
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// Permission to use, copy, modify, and/or distribute this software for any
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// purpose with or without fee is hereby granted, provided that the above
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// copyright notice and this permission notice appear in all copies.
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//
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// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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// This file describes the main pattern matcher setup (of three total) that
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// forms the `microchip_dsp` pass described in microchip_dsp.cc
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// At a high level, it works as follows:
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// ( 1) Starting from a DSP cell. Capture DSP configurations as states
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// ( 2) Match for pre-adder
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// ( 3) Match for post-adder
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// ( 4) Match register 'A', 'B', 'D', 'P'
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// ( 5) If post-adder and PREG both present, check if PREG feeds into post-adder.
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// This indicates an accumulator situation like the ASCII diagram below:
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// +--------------------------------+
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// |_________ |
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// | /-------\ +----+ |
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// +----+ +-| post- |___|PREG|---+ 'P'
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// |MULT|------ | adder | +----+
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// +----+ \-------/
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pattern microchip_dsp_pack
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state <SigBit> clock
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state <SigSpec> sigA sigB sigC sigD sigP
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state <Cell*> ffA ffB ffD ffP
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state <Cell*> preAdderStatic postAdderStatic
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state <bool> moveBtoA useFeedBack
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// static ports, used to detect dsp configuration
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state <SigSpec> bypassA bypassB bypassC bypassD bypassP
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state <SigSpec> bypassPASUB
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// Variables used for subpatterns
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state <SigSpec> argQ argD
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udata <bool> allowAsync
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udata <SigSpec> dffD dffQ
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udata <SigBit> dffclock
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udata <Cell*> dff
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udata <Cell*> u_preAdderStatic u_postAdderStatic
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udata <IdString> u_postAddAB
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state <IdString> postAddAB
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// (1) Starting from a DSP cell
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match dsp
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select dsp->type.in(\MACC_PA)
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endmatch
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// detect existing signals connected to DSP
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// detect configuration ports
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code sigA sigB sigC sigD clock sigP
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//helper function to remove unused bits
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auto unextend = [](const SigSpec &sig) {
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int i;
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for (i = GetSize(sig)-1; i > 0; i--)
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if (sig[i] != sig[i-1])
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break;
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// Do not remove non-const sign bit
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if (sig[i].wire)
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++i;
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return sig.extract(0, i);
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};
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//unextend to remove unused bits
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sigA = unextend(port(dsp, \A));
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sigB = unextend(port(dsp, \B));
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//update signals
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sigC = port(dsp, \C, SigSpec());
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sigD = port(dsp, \D, SigSpec());
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SigSpec P = port(dsp, \P);
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// Only care about bits that are used
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int i;
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for (i = GetSize(P)-1; i >= 0; i--)
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if (nusers(P[i]) > 1)
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break;
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i++;
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log_assert(nusers(P.extract_end(i)) <= 1);
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// This sigP could have no users if downstream sinks (e.g. $add) is
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// narrower than $mul result, for example
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if (i == 0)
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reject;
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sigP = P.extract(0, i);
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clock = port(dsp, \CLK, SigBit());
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endcode
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// capture static configuration ports
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code bypassA bypassB bypassC bypassD bypassPASUB bypassP
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bypassA = port(dsp, \A_BYPASS, SigSpec());
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bypassB = port(dsp, \B_BYPASS, SigSpec());
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bypassC = port(dsp, \C_BYPASS, SigSpec());
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bypassD = port(dsp, \D_BYPASS, SigSpec());
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bypassPASUB = port(dsp, \PASUB_BYPASS, SigSpec());
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bypassP = port(dsp, \P_BYPASS, SigSpec());
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endcode
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// (2) Match for pre-adder
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//
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code sigA sigB sigD preAdderStatic moveBtoA
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subpattern(preAddMatching);
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preAdderStatic = u_preAdderStatic;
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moveBtoA = false;
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if (preAdderStatic) {
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if (port(preAdderStatic, \Y) == sigA)
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{
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//used for packing
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moveBtoA = true;
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// sigA should be the input to the multiplier without the preAdd. sigB and sigD should be
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//the preAdd inputs. If our "A" input into the multiplier is from the preAdd (not sigA), then
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// we basically swap it.
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sigA = sigB;
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}
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// port B of preAdderStatic must be mapped to port D of DSP for subtraction
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sigD = port(preAdderStatic, \B);
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sigB = port(preAdderStatic, \A);
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}
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endcode
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// (3) Match for post-adder
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//
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code postAdderStatic sigP sigC
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u_postAdderStatic = nullptr;
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subpattern(postAddMatching);
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postAdderStatic = u_postAdderStatic;
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if (postAdderStatic) {
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//sigC will be whichever input to the postAdder that is NOT from the multiplier
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// u_postAddAB is the input to the postAdder from the multiplier
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sigC = port(postAdderStatic, u_postAddAB == \A ? \B : \A);
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sigP = port(postAdderStatic, \Y);
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}
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endcode
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// (4) Matching registers
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//
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// 'A' input for REG_A
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code argQ bypassA sigA clock ffA
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if (bypassA.is_fully_ones()){
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argQ = sigA;
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allowAsync = false;
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subpattern(in_dffe);
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if (dff) {
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ffA = dff;
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clock = dffclock;
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sigA = dffD;
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}
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}
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endcode
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// 'B' input for REG_B
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code argQ bypassB sigB clock ffB
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if (bypassB.is_fully_ones()){
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argQ = sigB;
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allowAsync = false;
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subpattern(in_dffe);
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if (dff) {
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ffB = dff;
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clock = dffclock;
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sigB = dffD;
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}
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}
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endcode
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// 'D' input for REG_D
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code argQ bypassP sigD clock ffD
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if (bypassD.is_fully_ones()){
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argQ = sigD;
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allowAsync = true;
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subpattern(in_dffe);
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if (dff) {
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ffD = dff;
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clock = dffclock;
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sigD = dffD;
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}
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}
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endcode
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// 'P' output for REG_P
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code argD ffP sigP clock bypassP
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if (bypassP.is_fully_ones() && nusers(sigP) == 2) {
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argD = sigP;
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allowAsync = false;
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subpattern(out_dffe);
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if (dff) {
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ffP = dff;
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clock = dffclock;
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sigP = dffQ;
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}
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}
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endcode
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// (5) If post-adder and PREG both present, check if PREG feeds into post-adder via port C.
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// This indicates an accumulator situation. Port C can be freed
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// +--------------------------------+
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// |_________ |
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// | /-------\ +----+ |
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// +----+ +-| post- |___|PREG|---+ 'P'
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// |MULT|------ | adder | +----+
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// +----+ \-------/
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code useFeedBack
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useFeedBack = false;
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if (postAdderStatic && ffP) {
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if (sigC == sigP) {
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useFeedBack = true;
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}
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}
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endcode
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// if any cells are absorbed, invoke the callback function
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code
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if (preAdderStatic || postAdderStatic)
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accept;
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if (ffA || ffB || ffD || ffP)
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accept;
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endcode
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// #######################
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// Subpattern for matching against post-adder
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// Match 'P' output that exclusively drives one of two inputs to an $add
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// cell (post-adder).
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// The other input to the adder is assumed to come in from the 'C' input
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subpattern postAddMatching
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arg sigP
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match postAdd
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select postAdd->type.in($add, $sub)
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select GetSize(port(postAdd, \Y)) <= 48
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// AB is the port that connects MUL to ADD
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choice <IdString> AB {\A, \B}
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select nusers(port(postAdd, AB)) == 2
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// has one input coming from multiplier
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index <SigBit> port(postAdd, AB)[0] === sigP[0]
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filter GetSize(port(postAdd, AB)) >= GetSize(sigP)
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filter port(postAdd, AB).extract(0, GetSize(sigP)) == sigP
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// Check that remainder of AB is a sign- or zero-extension
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filter port(postAdd, AB).extract_end(GetSize(sigP)) == SigSpec(sigP[GetSize(sigP)-1], GetSize(port(postAdd, AB))-GetSize(sigP)) || port(postAdd, AB).extract_end(GetSize(sigP)) == SigSpec(State::S0, GetSize(port(postAdd, AB))-GetSize(sigP))
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set postAddAB AB
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// optional
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endmatch
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code
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if (postAdd)
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{
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if (postAdd->type.in(ID($sub)) && postAddAB == \A) {
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// if $sub, the multiplier output must match to $sub.B, otherwise no match
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} else {
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u_postAddAB = postAddAB;
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u_postAdderStatic = postAdd;
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}
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}
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endcode
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// #######################
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// Subpattern for matching against pre-adder
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// support static PASUB only
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subpattern preAddMatching
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arg sigA sigB sigD bypassB bypassD bypassPASUB
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code
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u_preAdderStatic = nullptr;
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// Ensure that preAdder not already used
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// Assume we can inspect port D to see if its all zeros.
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if (!(sigD.empty() || sigD.is_fully_zero())) reject;
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if (!bypassB.is_fully_ones()) reject;
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if (!bypassD.is_fully_ones()) reject;
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if (!bypassPASUB.is_fully_ones()) reject;
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endcode
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match preAdd
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// can handle add or sub
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select preAdd->type.in($add, $sub)
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// Output has to be 18 bits or less, and only has single fanout
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select GetSize(port(preAdd, \Y)) <= 18
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select nusers(port(preAdd, \Y)) == 2
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// Adder inputs must be 18 bits or less
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select GetSize(port(preAdd, \A)) <= 18
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select GetSize(port(preAdd, \B)) <= 18
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// Output feeds into one of multiplier input
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filter port(preAdd, \Y) == sigB || port(preAdd, \Y) == sigA
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// optional
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endmatch
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code
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if (preAdd)
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{
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u_preAdderStatic = preAdd;
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}
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endcode
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// #######################
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// Subpattern for matching against input registers, based on knowledge of the
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// 'Q' input.
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subpattern in_dffe
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arg argQ clock
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code
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dff = nullptr;
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if (argQ.empty())
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reject;
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for (const auto &c : argQ.chunks()) {
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// Abandon matches when 'Q' is a constant
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if (!c.wire)
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reject;
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// Abandon matches when 'Q' has the keep attribute set
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if (c.wire->get_bool_attribute(\keep))
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reject;
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// Abandon matches when 'Q' has a non-zero init attribute set
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Const init = c.wire->attributes.at(\init, Const());
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if (!init.empty())
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for (auto b : init.extract(c.offset, c.width))
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if (b != State::Sx && b != State::S0)
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reject;
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}
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endcode
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match ff
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// reg D has async rst
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// reg A, B has sync rst
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select ff->type.in($dff, $dffe, $sdff, $sdffe, $adff, $adffe)
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// does not support clock inversion
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select param(ff, \CLK_POLARITY).as_bool()
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// it is possible that only part of a dff output matches argQ
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slice offset GetSize(port(ff, \D))
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index <SigBit> port(ff, \Q)[offset] === argQ[0]
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// Check that the rest of argQ is present
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filter GetSize(port(ff, \Q)) >= offset + GetSize(argQ)
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filter port(ff, \Q).extract(offset, GetSize(argQ)) == argQ
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// only consider async rst flops when flag is set
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filter !ff->type.in($adff, $adffe) || allowAsync
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// clock must be consistent
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filter clock == SigBit() || port(ff, \CLK)[0] == clock
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endmatch
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code argQ
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// Check that reset value, if present, is fully 0.
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bool noResetFlop = ff->type.in($dff, $dffe);
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bool srstZero = ff->type.in($sdff, $sdffe) && param(ff, \SRST_VALUE).is_fully_zero();
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bool arstZero = ff->type.in($adff, $adffe) && param(ff, \ARST_VALUE).is_fully_zero();
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bool resetLegal = noResetFlop || srstZero || arstZero;
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if (resetLegal)
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{
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SigSpec Q = port(ff, \Q);
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dff = ff;
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dffclock = port(ff, \CLK);
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dffD = argQ;
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SigSpec D = port(ff, \D);
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argQ = Q;
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dffD.replace(argQ, D);
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}
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endcode
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// #######################
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subpattern out_dffe
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arg argD argQ clock
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code
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dff = nullptr;
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for (auto c : argD.chunks())
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// Abandon matches when 'D' has the keep attribute set
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if (c.wire->get_bool_attribute(\keep))
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reject;
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endcode
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match ff
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select ff->type.in($dff, $dffe, $sdff, $sdffe)
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// does not support clock inversion
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select param(ff, \CLK_POLARITY).as_bool()
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slice offset GetSize(port(ff, \D))
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index <SigBit> port(ff, \D)[offset] === argD[0]
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// Check that the rest of argD is present
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filter GetSize(port(ff, \D)) >= offset + GetSize(argD)
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filter port(ff, \D).extract(offset, GetSize(argD)) == argD
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filter clock == SigBit() || port(ff, \CLK)[0] == clock
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endmatch
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code argQ
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SigSpec D = port(ff, \D);
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SigSpec Q = port(ff, \Q);
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argQ = argD;
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argQ.replace(D, Q);
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// Abandon matches when 'Q' has a non-zero init attribute set
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for (auto c : argQ.chunks()) {
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Const init = c.wire->attributes.at(\init, Const());
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if (!init.empty())
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for (auto b : init.extract(c.offset, c.width))
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if (b != State::Sx && b != State::S0)
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reject;
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}
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dff = ff;
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dffQ = argQ;
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dffclock = port(ff, \CLK);
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endcode
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