Icenowy Zheng c2b7ad3b28 anlogic: support BRAM mapping ... Anlogic FPGAs all have two kinds of BRAMs, one is 9bit*1K when being true dual port (or 18bit*512 when simple dual port), the other is 16bit*2K. Supports mapping of these two kinds of BRAMs. 9Kbit BRAM in SDP mode and 32Kbit BRAM with 8bit width are not support yet. Signed-off-by: Icenowy Zheng <icenowy@aosc.io>		2021-12-17 20:28:22 +08:00
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anlogic	anlogic: support BRAM mapping	2021-12-17 20:28:22 +08:00
common	Allow initial blocks to be disabled during tests	2021-11-13 21:53:25 +01:00
ecp5	abc9: replace cell type/parameters if derived type already processed (#2991)	2021-09-09 10:05:55 -07:00
efinix	tests: Centralize test collection and Makefile generation	2020-09-21 15:07:02 +02:00
gatemate	Add gitignore for gatemate	2021-12-03 09:56:37 +01:00
gowin	Gowin: deal with active-low tristate (#2971)	2021-08-20 21:21:06 +02:00
ice40	test/arch/{ecp5,ice40}/memories.ys: Use read_verilog -defer.	2021-08-11 14:52:38 +02:00
intel_alm	memory_bram: Reuse extract_rdff helper for make_outreg.	2021-05-25 22:42:03 +02:00
machxo2	iopadmap: Add native support for negative-polarity output enable.	2021-11-09 15:40:16 +01:00
nexus	memory_bram: Reuse extract_rdff helper for make_outreg.	2021-05-25 22:42:03 +02:00
quicklogic	quicklogic: ABC9 synthesis	2021-04-17 20:54:58 +02:00
xilinx	Fix the tests we just broke	2021-12-10 00:22:37 +01:00
run-test.sh	Add default assignments to SB_LUT4	2021-04-20 12:46:21 +02:00