mirror of https://github.com/YosysHQ/yosys.git
223 lines
6.7 KiB
C++
223 lines
6.7 KiB
C++
/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Claire Xenia Wolf <claire@yosyshq.com>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/yosys.h"
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#include "kernel/sigtools.h"
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#include "kernel/mem.h"
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#include "kernel/ff.h"
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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struct OptMemPass : public Pass {
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OptMemPass() : Pass("opt_mem", "optimize memories") { }
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void help() override
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" opt_mem [options] [selection]\n");
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log("\n");
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log("This pass performs various optimizations on memories in the design.\n");
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log("\n");
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}
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void execute(std::vector<std::string> args, RTLIL::Design *design) override
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{
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log_header(design, "Executing OPT_MEM pass (optimize memories).\n");
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++) {
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// if (args[argidx] == "-nomux") {
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// mode_nomux = true;
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// continue;
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// }
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break;
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}
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extra_args(args, argidx, design);
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int total_count = 0;
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for (auto module : design->selected_modules()) {
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SigMap sigmap(module);
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FfInitVals initvals(&sigmap, module);
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for (auto &mem : Mem::get_selected_memories(module)) {
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std::vector<bool> always_0(mem.width, true);
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std::vector<bool> always_1(mem.width, true);
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bool changed = false;
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for (auto &port : mem.wr_ports) {
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if (port.en.is_fully_zero()) {
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port.removed = true;
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changed = true;
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total_count++;
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} else {
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for (int sub = 0; sub < (1 << port.wide_log2); sub++) {
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for (int i = 0; i < mem.width; i++) {
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int bit = sub * mem.width + i;
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if (port.en[bit] != State::S0) {
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if (port.data[bit] != State::Sx && port.data[bit] != State::S0) {
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always_0[i] = false;
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}
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if (port.data[bit] != State::Sx && port.data[bit] != State::S1) {
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always_1[i] = false;
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}
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} else {
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if (port.data[bit] != State::Sx) {
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port.data[bit] = State::Sx;
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changed = true;
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total_count++;
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}
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}
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}
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}
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}
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}
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for (auto &init : mem.inits) {
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for (int i = 0; i < GetSize(init.data); i++) {
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State bit = init.data.bits[i];
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int lane = i % mem.width;
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if (bit != State::Sx && bit != State::S0) {
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always_0[lane] = false;
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}
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if (bit != State::Sx && bit != State::S1) {
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always_1[lane] = false;
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}
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}
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}
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std::vector<int> swizzle;
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for (int i = 0; i < mem.width; i++) {
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if (!always_0[i] && !always_1[i]) {
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swizzle.push_back(i);
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continue;
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}
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State bit;
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if (!always_0[i]) {
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log("%s.%s: removing const-1 lane %d\n", log_id(module->name), log_id(mem.memid), i);
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bit = State::S1;
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} else if (!always_1[i]) {
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log("%s.%s: removing const-0 lane %d\n", log_id(module->name), log_id(mem.memid), i);
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bit = State::S0;
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} else {
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log("%s.%s: removing const-x lane %d\n", log_id(module->name), log_id(mem.memid), i);
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bit = State::Sx;
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}
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// Reconnect read port data.
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for (auto &port: mem.rd_ports) {
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for (int sub = 0; sub < (1 << port.wide_log2); sub++) {
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int bidx = sub * mem.width + i;
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if (!port.clk_enable) {
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module->connect(port.data[bidx], bit);
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} else {
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// The FF will most likely be redundant, but it's up to opt_dff to deal with this.
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FfData ff(module, &initvals, NEW_ID);
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ff.width = 1;
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ff.has_clk = true;
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ff.sig_clk = port.clk;
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ff.pol_clk = port.clk_polarity;
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if (port.en != State::S1) {
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ff.has_ce = true;
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ff.pol_ce = true;
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ff.sig_ce = port.en;
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}
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if (port.arst != State::S0) {
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ff.has_arst = true;
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ff.pol_arst = true;
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ff.sig_arst = port.arst;
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ff.val_arst = port.arst_value[bidx];
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}
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if (port.srst != State::S0) {
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ff.has_srst = true;
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ff.pol_srst = true;
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ff.sig_srst = port.srst;
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ff.val_srst = port.srst_value[bidx];
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}
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ff.sig_d = bit;
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ff.sig_q = port.data[bidx];
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ff.val_init = port.init_value[bidx];
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ff.emit();
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}
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}
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}
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}
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if (GetSize(swizzle) == 0) {
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mem.remove();
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total_count++;
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continue;
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}
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if (GetSize(swizzle) != mem.width) {
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for (auto &port: mem.wr_ports) {
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SigSpec new_data;
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SigSpec new_en;
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for (int sub = 0; sub < (1 << port.wide_log2); sub++) {
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for (auto i: swizzle) {
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new_data.append(port.data[sub * mem.width + i]);
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new_en.append(port.en[sub * mem.width + i]);
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}
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}
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port.data = new_data;
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port.en = new_en;
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}
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for (auto &port: mem.rd_ports) {
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SigSpec new_data;
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Const new_init;
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Const new_arst;
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Const new_srst;
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for (int sub = 0; sub < (1 << port.wide_log2); sub++) {
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for (auto i: swizzle) {
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int bidx = sub * mem.width + i;
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new_data.append(port.data[bidx]);
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new_init.bits.push_back(port.init_value.bits[bidx]);
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new_arst.bits.push_back(port.arst_value.bits[bidx]);
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new_srst.bits.push_back(port.srst_value.bits[bidx]);
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}
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}
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port.data = new_data;
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port.init_value = new_init;
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port.arst_value = new_arst;
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port.srst_value = new_srst;
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}
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for (auto &init: mem.inits) {
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Const new_data;
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Const new_en;
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for (int s = 0; s < GetSize(init.data); s += mem.width) {
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for (auto i: swizzle) {
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new_data.bits.push_back(init.data.bits[s + i]);
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}
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}
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for (auto i: swizzle) {
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new_en.bits.push_back(init.en.bits[i]);
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}
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init.data = new_data;
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init.en = new_en;
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}
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mem.width = GetSize(swizzle);
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changed = true;
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total_count++;
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}
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if (changed) {
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mem.emit();
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}
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}
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}
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if (total_count)
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design->scratchpad_set_bool("opt.did_something", true);
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log("Performed a total of %d transformations.\n", total_count);
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}
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} OptMemPass;
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PRIVATE_NAMESPACE_END
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