yosys/passes
Clifford Wolf eb1e3caae7 Fixed "flatten" for unconnected inout ports 2015-10-13 10:30:23 +02:00
..
cmds Added edgetypes command 2015-09-27 11:53:20 +02:00
equiv Spell check (by Larry Doolittle) 2015-08-14 10:56:05 +02:00
fsm Do not detect fsm state registers with init attribute 2015-09-21 11:54:00 +02:00
hierarchy Spell check (by Larry Doolittle) 2015-08-14 10:56:05 +02:00
memory Bugfix in bram read-enable code 2015-09-25 14:22:33 +02:00
opt Added wreduce $mul support and fixed signed $mul opt_const bug 2015-09-25 17:27:06 +02:00
proc Re-created command-reference-manual.tex, copied some doc fixes to online help 2015-08-14 11:27:19 +02:00
sat Added sat -show-regs, -show-public, -show-all 2015-08-18 17:14:30 +02:00
techmap Fixed "flatten" for unconnected inout ports 2015-10-13 10:30:23 +02:00
tests Added "test_cell -noeval" 2015-09-25 17:27:18 +02:00