Clifford Wolf 76f20492a4 Merge pull request #1162 from whitequark/rtlil-case-attrs ... Allow attributes on individual switch cases in RTLIL		2019-07-09 18:48:38 +01:00
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aiger	Fix spacing from spaces to tabs	2019-06-07 15:44:57 -07:00
ast	Add "read_verilog -pwires" feature, closes #1106	2019-06-19 14:38:50 +02:00
blif	Add missing "[options]" to read_blif help	2019-02-08 12:41:39 -08:00
ilang	Merge pull request #1162 from whitequark/rtlil-case-attrs	2019-07-09 18:48:38 +01:00
json	Add upto and offset to JSON ports	2019-06-21 19:47:25 +02:00
liberty	Fix typographical and grammatical errors and inconsistencies.	2019-01-02 13:12:17 +00:00
verific	Only support Symbiotic EDA flavored Verific	2019-06-02 10:14:50 +02:00
verilog	Merge pull request #1147 from YosysHQ/clifford/fix1144	2019-07-09 18:47:08 +01:00