yosys/frontends/verilog
Clifford Wolf e275e8eef9 Add support for cell arrays 2014-06-07 11:48:50 +02:00
..
.gitignore added .gitignore files 2013-01-05 11:19:11 +01:00
Makefile.inc Various improvements in support for generate statements 2013-12-04 21:06:54 +01:00
const2ast.cc Fixed handling of unsized constants in verilog frontend 2014-01-24 15:05:24 +01:00
lexer.l added while and repeat support to verilog parser 2014-06-06 17:40:04 +02:00
parser.y Add support for cell arrays 2014-06-07 11:48:50 +02:00
preproc.cc Added Verilog support for "`default_nettype none" 2014-02-17 14:28:52 +01:00
verilog_frontend.cc Improved error message for options after front-end filename arguments 2014-06-04 09:10:50 +02:00
verilog_frontend.h Added Verilog support for "`default_nettype none" 2014-02-17 14:28:52 +01:00