yosys/techlibs
Eddie Hung 726e2da8f2 Merge branch 'map_cells_before_map_luts' into xc7srl 2019-04-21 14:28:55 -07:00
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achronix Reduce amount of trailing whitespace in code base 2019-02-28 14:58:11 -08:00
anlogic Reduce amount of trailing whitespace in code base 2019-02-28 14:58:11 -08:00
common Merge pull request #772 from whitequark/synth_lut 2019-01-02 15:44:57 +01:00
coolrunner2 Unify usage of noflatten among architectures 2019-01-04 11:37:25 +01:00
easic Fix typographical and grammatical errors and inconsistencies. 2019-01-02 13:12:17 +00:00
ecp5 Revert "synth_* with -retime option now calls abc with -D 1 as well" 2019-04-18 07:59:16 -07:00
gowin Revert "synth_* with -retime option now calls abc with -D 1 as well" 2019-04-18 07:59:16 -07:00
greenpak4 Revert "synth_* with -retime option now calls abc with -D 1 as well" 2019-04-18 07:59:16 -07:00
ice40 Remove ice40/cells_sim.v hack to avoid warning for blocking memory writes 2019-03-12 20:14:18 +01:00
intel Fixing issues in CycloneV cell sim 2019-04-11 19:59:03 -05:00
sf2 Revert "synth_* with -retime option now calls abc with -D 1 as well" 2019-04-18 07:59:16 -07:00
xilinx Merge branch 'map_cells_before_map_luts' into xc7srl 2019-04-21 14:28:55 -07:00
.gitignore added .gitignore files 2013-01-05 11:19:11 +01:00