mirror of https://github.com/YosysHQ/yosys.git
This isn't actually necessary anymore after scheduling was improved, and `clean -purge` disrupts the mapping between wires in the input RTLIL netlist and the output CXXRTL code. |
||
---|---|---|
.. | ||
aiger | ||
blif | ||
btor | ||
cxxrtl | ||
edif | ||
firrtl | ||
ilang | ||
intersynth | ||
json | ||
protobuf | ||
simplec | ||
smt2 | ||
smv | ||
spice | ||
table | ||
verilog |