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riscv
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yosys
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https://github.com/YosysHQ/yosys.git
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6b34215efd
yosys
/
techlibs
/
common
History
Clifford Wolf
b17d6531c8
Added "make PRETTY=1"
2014-07-24 17:15:01 +02:00
..
Makefile.inc
Added "make PRETTY=1"
2014-07-24 17:15:01 +02:00
blackbox.sed
Renamed stdcells_sim.v to simcells.v and fixed blackbox.v
2013-11-24 20:44:00 +01:00
pmux2mux.v
Added techlibs/common/pmux2mux.v
2014-01-17 20:06:15 +01:00
simcells.v
Added support for dlatchsr cells
2014-03-31 14:14:40 +02:00
simlib.v
Fixed simlib.v model for $mem
2014-07-17 16:48:36 +02:00
stdcells.v
Fixes for improved techmap of shifts with large B inputs
2014-03-06 13:33:12 +01:00