yosys/frontends/ast
Kamil Rakoczy 61501e3266 Fix input/output attributes when resolving typedef of wire
Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
2021-01-18 17:31:22 +01:00
..
Makefile.inc Added Verilog/AST support for DPI functions (dpi_call() still unimplemented) 2014-08-21 12:43:51 +02:00
ast.cc Return correct modname when found in cache. 2020-11-26 13:31:22 +01:00
ast.h verilog: improved support for recursive functions 2020-12-31 18:33:59 -07:00
dpicall.cc Fixed trailing whitespaces 2015-07-02 11:14:30 +02:00
genrtlil.cc genrtlil: fix mux2rtlil generated wire signedness 2020-12-22 17:49:16 -07:00
simplify.cc Fix input/output attributes when resolving typedef of wire 2021-01-18 17:31:22 +01:00