Claire Xenia Wolf acad7a6e40 Switch verific bindings from Symbiotic EDA flavored Verific to YosysHQ flavored Verific ... Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>		2021-01-20 20:48:10 +01:00
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aiger	Remove YS_ATTRIBUTE(unused) where present just for log_assert()/log_debug().	2020-06-19 15:48:58 +00:00
ast	Fix input/output attributes when resolving typedef of wire	2021-01-18 17:31:22 +01:00
blif	Use C++11 final/override keywords.	2020-06-18 23:34:52 +00:00
json	Use C++11 final/override keywords.	2020-06-18 23:34:52 +00:00
liberty	Use C++11 final/override keywords.	2020-06-18 23:34:52 +00:00
rpc	Fix argument handling in connect_rpc	2020-10-19 13:40:57 +02:00
rtlil	rtlil: remove dotted identifiers.	2020-11-25 16:47:20 +00:00
verific	Switch verific bindings from Symbiotic EDA flavored Verific to YosysHQ flavored Verific	2021-01-20 20:48:10 +01:00
verilog	sv: fix support wire and var data type modifiers	2021-01-20 09:16:21 -07:00