mirror of https://github.com/YosysHQ/yosys.git
697 lines
24 KiB
C++
697 lines
24 KiB
C++
/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/compatibility.h"
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#include "kernel/register.h"
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#include "kernel/sigtools.h"
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#include "kernel/log.h"
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#include <stdlib.h>
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#include <assert.h>
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#include <stdio.h>
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#include <string.h>
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#include "passes/techmap/stdcells.inc"
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// see simplemap.cc
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extern void simplemap_get_mappers(std::map<std::string, void(*)(RTLIL::Module*, RTLIL::Cell*)> &mappers);
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static void apply_prefix(std::string prefix, std::string &id)
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{
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if (id[0] == '\\')
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id = prefix + "." + id.substr(1);
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else
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id = "$techmap" + prefix + "." + id;
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}
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static void apply_prefix(std::string prefix, RTLIL::SigSpec &sig, RTLIL::Module *module)
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{
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std::vector<RTLIL::SigChunk> chunks = sig;
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for (auto &chunk : chunks)
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if (chunk.wire != NULL) {
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std::string wire_name = chunk.wire->name;
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apply_prefix(prefix, wire_name);
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assert(module->wires_.count(wire_name) > 0);
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chunk.wire = module->wires_[wire_name];
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}
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sig = chunks;
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}
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struct TechmapWorker
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{
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std::map<std::string, void(*)(RTLIL::Module*, RTLIL::Cell*)> simplemap_mappers;
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std::map<std::pair<RTLIL::IdString, std::map<RTLIL::IdString, RTLIL::Const>>, RTLIL::Module*> techmap_cache;
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std::map<RTLIL::Module*, bool> techmap_do_cache;
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struct TechmapWireData {
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RTLIL::Wire *wire;
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RTLIL::SigSpec value;
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};
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typedef std::map<std::string, std::vector<TechmapWireData>> TechmapWires;
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TechmapWires techmap_find_special_wires(RTLIL::Module *module)
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{
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TechmapWires result;
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if (module == NULL)
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return result;
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for (auto &it : module->wires_) {
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const char *p = it.first.c_str();
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if (*p == '$')
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continue;
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const char *q = strrchr(p+1, '.');
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p = q ? q : p+1;
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if (!strncmp(p, "_TECHMAP_", 9)) {
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TechmapWireData record;
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record.wire = it.second;
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record.value = it.second;
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result[p].push_back(record);
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it.second->attributes["\\keep"] = RTLIL::Const(1);
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it.second->attributes["\\_techmap_special_"] = RTLIL::Const(1);
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}
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}
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if (!result.empty()) {
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SigMap sigmap(module);
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for (auto &it1 : result)
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for (auto &it2 : it1.second)
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sigmap.apply(it2.value);
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}
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return result;
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}
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void techmap_module_worker(RTLIL::Design *design, RTLIL::Module *module, RTLIL::Cell *cell, RTLIL::Module *tpl, bool flatten_mode)
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{
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log("Mapping `%s.%s' using `%s'.\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(cell->name), RTLIL::id2cstr(tpl->name));
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if (tpl->memories.size() != 0)
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log_error("Technology map yielded memories -> this is not supported.\n");
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if (tpl->processes.size() != 0) {
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log("Technology map yielded processes:\n");
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for (auto &it : tpl->processes)
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log(" %s",RTLIL::id2cstr(it.first));
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log_error("Technology map yielded processes -> this is not supported.\n");
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}
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std::string orig_cell_name;
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if (!flatten_mode)
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for (auto &it : tpl->cells_)
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if (it.first == "\\_TECHMAP_REPLACE_") {
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orig_cell_name = cell->name;
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module->rename(cell, stringf("$techmap%d", RTLIL::autoidx++) + cell->name);
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break;
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}
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std::map<RTLIL::IdString, RTLIL::IdString> positional_ports;
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for (auto &it : tpl->wires_) {
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if (it.second->port_id > 0)
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positional_ports[stringf("$%d", it.second->port_id)] = it.first;
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std::string w_name = it.second->name;
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apply_prefix(cell->name, w_name);
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RTLIL::Wire *w = module->addWire(w_name, it.second);
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w->port_input = false;
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w->port_output = false;
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w->port_id = 0;
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if (it.second->get_bool_attribute("\\_techmap_special_"))
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w->attributes.clear();
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design->select(module, w);
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}
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SigMap port_signal_map;
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for (auto &it : cell->connections()) {
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RTLIL::IdString portname = it.first;
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if (positional_ports.count(portname) > 0)
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portname = positional_ports.at(portname);
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if (tpl->wires_.count(portname) == 0 || tpl->wires_.at(portname)->port_id == 0) {
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if (portname.substr(0, 1) == "$")
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log_error("Can't map port `%s' of cell `%s' to template `%s'!\n", portname.c_str(), cell->name.c_str(), tpl->name.c_str());
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continue;
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}
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RTLIL::Wire *w = tpl->wires_.at(portname);
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RTLIL::SigSig c;
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if (w->port_output) {
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c.first = it.second;
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c.second = RTLIL::SigSpec(w);
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apply_prefix(cell->name, c.second, module);
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} else {
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c.first = RTLIL::SigSpec(w);
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c.second = it.second;
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apply_prefix(cell->name, c.first, module);
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}
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if (c.second.size() > c.first.size())
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c.second.remove(c.first.size(), c.second.size() - c.first.size());
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if (c.second.size() < c.first.size())
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c.second.append(RTLIL::SigSpec(RTLIL::State::S0, c.first.size() - c.second.size()));
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assert(c.first.size() == c.second.size());
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if (flatten_mode) {
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// more conservative approach:
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// connect internal and external wires
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module->connect(c);
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} else {
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// approach that yields nicer outputs:
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// replace internal wires that are connected to external wires
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if (w->port_output)
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port_signal_map.add(c.second, c.first);
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else
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port_signal_map.add(c.first, c.second);
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}
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}
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for (auto &it : tpl->cells_)
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{
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RTLIL::IdString c_name = it.second->name;
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if (!flatten_mode && c_name == "\\_TECHMAP_REPLACE_")
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c_name = orig_cell_name;
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else
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apply_prefix(cell->name, c_name);
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RTLIL::Cell *c = module->addCell(c_name, it.second);
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design->select(module, c);
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if (!flatten_mode && c->type.substr(0, 2) == "\\$")
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c->type = c->type.substr(1);
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for (auto &it2 : c->connections_) {
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apply_prefix(cell->name, it2.second, module);
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port_signal_map.apply(it2.second);
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}
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}
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for (auto &it : tpl->connections()) {
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RTLIL::SigSig c = it;
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apply_prefix(cell->name, c.first, module);
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apply_prefix(cell->name, c.second, module);
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port_signal_map.apply(c.first);
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port_signal_map.apply(c.second);
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module->connect(c);
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}
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module->remove(cell);
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}
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bool techmap_module(RTLIL::Design *design, RTLIL::Module *module, RTLIL::Design *map, std::set<RTLIL::Cell*> &handled_cells,
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const std::map<RTLIL::IdString, std::set<RTLIL::IdString>> &celltypeMap, bool flatten_mode)
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{
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if (!design->selected(module))
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return false;
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bool log_continue = false;
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bool did_something = false;
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std::vector<std::string> cell_names;
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SigMap sigmap(module);
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for (auto &cell_it : module->cells_)
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cell_names.push_back(cell_it.first);
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for (auto &cell_name : cell_names)
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{
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if (module->cells_.count(cell_name) == 0)
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continue;
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RTLIL::Cell *cell = module->cells_[cell_name];
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if (!design->selected(module, cell) || handled_cells.count(cell) > 0)
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continue;
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if (celltypeMap.count(cell->type) == 0)
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continue;
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for (auto &tpl_name : celltypeMap.at(cell->type))
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{
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std::string derived_name = tpl_name;
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RTLIL::Module *tpl = map->modules_[tpl_name];
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std::map<RTLIL::IdString, RTLIL::Const> parameters = cell->parameters;
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if (tpl->get_bool_attribute("\\blackbox"))
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continue;
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if (!flatten_mode)
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{
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if (tpl->get_bool_attribute("\\techmap_simplemap")) {
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log("Mapping %s.%s (%s) with simplemap.\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(cell->name), RTLIL::id2cstr(cell->type));
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if (simplemap_mappers.count(cell->type) == 0)
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log_error("No simplemap mapper for cell type %s found!\n", RTLIL::id2cstr(cell->type));
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simplemap_mappers.at(cell->type)(module, cell);
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module->remove(cell);
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cell = NULL;
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did_something = true;
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break;
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}
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for (auto conn : cell->connections()) {
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if (conn.first.substr(0, 1) == "$")
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continue;
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if (tpl->wires_.count(conn.first) > 0 && tpl->wires_.at(conn.first)->port_id > 0)
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continue;
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if (!conn.second.is_fully_const() || parameters.count(conn.first) > 0 || tpl->avail_parameters.count(conn.first) == 0)
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goto next_tpl;
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parameters[conn.first] = conn.second.as_const();
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}
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if (0) {
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next_tpl:
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continue;
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}
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if (tpl->avail_parameters.count("\\_TECHMAP_CELLTYPE_") != 0)
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parameters["\\_TECHMAP_CELLTYPE_"] = RTLIL::unescape_id(cell->type);
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for (auto conn : cell->connections()) {
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if (tpl->avail_parameters.count(stringf("\\_TECHMAP_CONSTMSK_%s_", RTLIL::id2cstr(conn.first))) != 0) {
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std::vector<RTLIL::SigBit> v = sigmap(conn.second).to_sigbit_vector();
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for (auto &bit : v)
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bit = RTLIL::SigBit(bit.wire == NULL ? RTLIL::State::S1 : RTLIL::State::S0);
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parameters[stringf("\\_TECHMAP_CONSTMSK_%s_", RTLIL::id2cstr(conn.first))] = RTLIL::SigSpec(v).as_const();
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}
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if (tpl->avail_parameters.count(stringf("\\_TECHMAP_CONSTVAL_%s_", RTLIL::id2cstr(conn.first))) != 0) {
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std::vector<RTLIL::SigBit> v = sigmap(conn.second).to_sigbit_vector();
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for (auto &bit : v)
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if (bit.wire != NULL)
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bit = RTLIL::SigBit(RTLIL::State::Sx);
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parameters[stringf("\\_TECHMAP_CONSTVAL_%s_", RTLIL::id2cstr(conn.first))] = RTLIL::SigSpec(v).as_const();
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}
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}
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int unique_bit_id_counter = 0;
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std::map<RTLIL::SigBit, int> unique_bit_id;
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unique_bit_id[RTLIL::State::S0] = unique_bit_id_counter++;
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unique_bit_id[RTLIL::State::S1] = unique_bit_id_counter++;
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unique_bit_id[RTLIL::State::Sx] = unique_bit_id_counter++;
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unique_bit_id[RTLIL::State::Sz] = unique_bit_id_counter++;
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for (auto conn : cell->connections())
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if (tpl->avail_parameters.count(stringf("\\_TECHMAP_CONNMAP_%s_", RTLIL::id2cstr(conn.first))) != 0) {
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for (auto &bit : sigmap(conn.second).to_sigbit_vector())
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if (unique_bit_id.count(bit) == 0)
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unique_bit_id[bit] = unique_bit_id_counter++;
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}
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int bits = 0;
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for (int i = 0; i < 32; i++)
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if (((unique_bit_id_counter-1) & (1 << i)) != 0)
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bits = i;
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if (tpl->avail_parameters.count("\\_TECHMAP_BITS_CONNMAP_"))
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parameters["\\_TECHMAP_BITS_CONNMAP_"] = bits;
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for (auto conn : cell->connections())
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if (tpl->avail_parameters.count(stringf("\\_TECHMAP_CONNMAP_%s_", RTLIL::id2cstr(conn.first))) != 0) {
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RTLIL::Const value;
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for (auto &bit : sigmap(conn.second).to_sigbit_vector()) {
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RTLIL::Const chunk(unique_bit_id.at(bit), bits);
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value.bits.insert(value.bits.end(), chunk.bits.begin(), chunk.bits.end());
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}
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parameters[stringf("\\_TECHMAP_CONNMAP_%s_", RTLIL::id2cstr(conn.first))] = value;
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}
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}
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std::pair<RTLIL::IdString, std::map<RTLIL::IdString, RTLIL::Const>> key(tpl_name, parameters);
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if (techmap_cache.count(key) > 0) {
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tpl = techmap_cache[key];
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} else {
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if (cell->parameters.size() != 0) {
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derived_name = tpl->derive(map, parameters);
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tpl = map->modules_[derived_name];
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log_continue = true;
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}
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techmap_cache[key] = tpl;
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}
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if (flatten_mode)
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techmap_do_cache[tpl] = true;
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if (techmap_do_cache.count(tpl) == 0)
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{
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bool keep_running = true;
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techmap_do_cache[tpl] = true;
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std::set<std::string> techmap_wire_names;
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while (keep_running)
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{
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TechmapWires twd = techmap_find_special_wires(tpl);
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keep_running = false;
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for (auto &it : twd)
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techmap_wire_names.insert(it.first);
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for (auto &it : twd["_TECHMAP_FAIL_"]) {
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RTLIL::SigSpec value = it.value;
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if (value.is_fully_const() && value.as_bool()) {
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log("Not using module `%s' from techmap as it contains a %s marker wire with non-zero value %s.\n",
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derived_name.c_str(), RTLIL::id2cstr(it.wire->name), log_signal(value));
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techmap_do_cache[tpl] = false;
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}
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}
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if (!techmap_do_cache[tpl])
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break;
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for (auto &it : twd)
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{
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if (it.first.substr(0, 12) != "_TECHMAP_DO_" || it.second.empty())
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continue;
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auto &data = it.second.front();
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if (!data.value.is_fully_const())
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log_error("Techmap yielded config wire %s with non-const value %s.\n", RTLIL::id2cstr(data.wire->name), log_signal(data.value));
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techmap_wire_names.erase(it.first);
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const char *p = data.wire->name.c_str();
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const char *q = strrchr(p+1, '.');
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q = q ? q : p+1;
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assert(!strncmp(q, "_TECHMAP_DO_", 12));
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std::string new_name = data.wire->name.substr(0, q-p) + "_TECHMAP_DONE_" + data.wire->name.substr(q-p+12);
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while (tpl->wires_.count(new_name))
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new_name += "_";
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tpl->rename(data.wire, new_name);
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std::string cmd_string = data.value.as_const().decode_string();
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Pass::call_on_module(map, tpl, cmd_string);
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keep_running = true;
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break;
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}
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}
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TechmapWires twd = techmap_find_special_wires(tpl);
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for (auto &it : twd) {
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if (it.first != "_TECHMAP_FAIL_" && it.first.substr(0, 12) != "_TECHMAP_DO_" && it.first.substr(0, 14) != "_TECHMAP_DONE_")
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log_error("Techmap yielded unknown config wire %s.\n", it.first.c_str());
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if (techmap_do_cache[tpl])
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for (auto &it2 : it.second)
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if (!it2.value.is_fully_const())
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log_error("Techmap yielded config wire %s with non-const value %s.\n", RTLIL::id2cstr(it2.wire->name), log_signal(it2.value));
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techmap_wire_names.erase(it.first);
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}
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for (auto &it : techmap_wire_names)
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log_error("Techmap special wire %s disappeared. This is considered a fatal error.\n", RTLIL::id2cstr(it));
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}
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if (techmap_do_cache.at(tpl) == false)
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continue;
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if (log_continue) {
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log_header("Continuing TECHMAP pass.\n");
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log_continue = false;
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}
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techmap_module_worker(design, module, cell, tpl, flatten_mode);
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did_something = true;
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cell = NULL;
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break;
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}
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handled_cells.insert(cell);
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}
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if (log_continue) {
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log_header("Continuing TECHMAP pass.\n");
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log_continue = false;
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}
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return did_something;
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}
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};
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struct TechmapPass : public Pass {
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TechmapPass() : Pass("techmap", "generic technology mapper") { }
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virtual void help()
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" techmap [-map filename] [selection]\n");
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|
log("\n");
|
|
log("This pass implements a very simple technology mapper that replaces cells in\n");
|
|
log("the design with implementations given in form of a verilog or ilang source\n");
|
|
log("file.\n");
|
|
log("\n");
|
|
log(" -map filename\n");
|
|
log(" the library of cell implementations to be used.\n");
|
|
log(" without this parameter a builtin library is used that\n");
|
|
log(" transforms the internal RTL cells to the internal gate\n");
|
|
log(" library.\n");
|
|
log("\n");
|
|
log(" -share_map filename\n");
|
|
log(" like -map, but look for the file in the share directory (where the\n");
|
|
log(" yosys data files are). this is mainly used internally when techmap\n");
|
|
log(" is called from other commands.\n");
|
|
log("\n");
|
|
log(" -max_iter <number>\n");
|
|
log(" only run the specified number of iterations.\n");
|
|
log("\n");
|
|
log(" -D <define>, -I <incdir>\n");
|
|
log(" this options are passed as-is to the verilog frontend for loading the\n");
|
|
log(" map file. Note that the verilog frontend is also called with the\n");
|
|
log(" '-ignore_redef' option set.\n");
|
|
log("\n");
|
|
log("When a module in the map file has the 'techmap_celltype' attribute set, it will\n");
|
|
log("match cells with a type that match the text value of this attribute. Otherwise\n");
|
|
log("the module name will be used to match the cell.\n");
|
|
log("\n");
|
|
log("When a module in the map file has the 'techmap_simplemap' attribute set, techmap\n");
|
|
log("will use 'simplemap' (see 'help simplemap') to map cells matching the module.\n");
|
|
log("\n");
|
|
log("All wires in the modules from the map file matching the pattern _TECHMAP_*\n");
|
|
log("or *._TECHMAP_* are special wires that are used to pass instructions from\n");
|
|
log("the mapping module to the techmap command. At the moment the following special\n");
|
|
log("wires are supported:\n");
|
|
log("\n");
|
|
log(" _TECHMAP_FAIL_\n");
|
|
log(" When this wire is set to a non-zero constant value, techmap will not\n");
|
|
log(" use this module and instead try the next module with a matching\n");
|
|
log(" 'techmap_celltype' attribute.\n");
|
|
log("\n");
|
|
log(" When such a wire exists but does not have a constant value after all\n");
|
|
log(" _TECHMAP_DO_* commands have been executed, an error is generated.\n");
|
|
log("\n");
|
|
log(" _TECHMAP_DO_*\n");
|
|
log(" This wires are evaluated in alphabetical order. The constant text value\n");
|
|
log(" of this wire is a yosys command (or sequence of commands) that is run\n");
|
|
log(" by techmap on the module. A common use case is to run 'proc' on modules\n");
|
|
log(" that are written using always-statements.\n");
|
|
log("\n");
|
|
log(" When such a wire has a non-constant value at the time it is to be\n");
|
|
log(" evaluated, an error is produced. That means it is possible for such a\n");
|
|
log(" wire to start out as non-constant and evaluate to a constant value\n");
|
|
log(" during processing of other _TECHMAP_DO_* commands.\n");
|
|
log("\n");
|
|
log("In addition to this special wires, techmap also supports special parameters in\n");
|
|
log("modules in the map file:\n");
|
|
log("\n");
|
|
log(" _TECHMAP_CELLTYPE_\n");
|
|
log(" When a parameter with this name exists, it will be set to the type name\n");
|
|
log(" of the cell that matches the module.\n");
|
|
log("\n");
|
|
log(" _TECHMAP_CONSTMSK_<port-name>_\n");
|
|
log(" _TECHMAP_CONSTVAL_<port-name>_\n");
|
|
log(" When this pair of parameters is available in a module for a port, then\n");
|
|
log(" former has a 1-bit for each constant input bit and the latter has the\n");
|
|
log(" value for this bit. The unused bits of the latter are set to undef (x).\n");
|
|
log("\n");
|
|
log(" _TECHMAP_BITS_CONNMAP_\n");
|
|
log(" _TECHMAP_CONNMAP_<port-name>_\n");
|
|
log(" For an N-bit port, the _TECHMAP_CONNMAP_<port-name>_ parameter, if it\n");
|
|
log(" exists, will be set to an N*_TECHMAP_BITS_CONNMAP_ bit vector containing\n");
|
|
log(" N words (of _TECHMAP_BITS_CONNMAP_ bits each) that assign each single\n");
|
|
log(" bit driver a unique id. The values 0-3 are reserved for 0, 1, x, and z.\n");
|
|
log(" This can be used to detect shorted inputs.\n");
|
|
log("\n");
|
|
log("When a module in the map file has a parameter where the according cell in the\n");
|
|
log("design has a port, the module from the map file is only used if the port in\n");
|
|
log("the design is connected to a constant value. The parameter is then set to the\n");
|
|
log("constant value.\n");
|
|
log("\n");
|
|
log("A cell with the name _TECHMAP_REPLACE_ in the map file will inherit the name\n");
|
|
log("of the cell that is beeing replaced.\n");
|
|
log("\n");
|
|
log("See 'help extract' for a pass that does the opposite thing.\n");
|
|
log("\n");
|
|
log("See 'help flatten' for a pass that does flatten the design (which is\n");
|
|
log("esentially techmap but using the design itself as map library).\n");
|
|
log("\n");
|
|
}
|
|
virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
|
|
{
|
|
log_header("Executing TECHMAP pass (map to technology primitives).\n");
|
|
log_push();
|
|
|
|
std::vector<std::string> map_files;
|
|
std::string verilog_frontend = "verilog -ignore_redef";
|
|
int max_iter = -1;
|
|
|
|
size_t argidx;
|
|
std::string proc_share_path = proc_share_dirname();
|
|
for (argidx = 1; argidx < args.size(); argidx++) {
|
|
if (args[argidx] == "-map" && argidx+1 < args.size()) {
|
|
map_files.push_back(args[++argidx]);
|
|
continue;
|
|
}
|
|
if (args[argidx] == "-share_map" && argidx+1 < args.size()) {
|
|
map_files.push_back(proc_share_path + args[++argidx]);
|
|
continue;
|
|
}
|
|
if (args[argidx] == "-max_iter" && argidx+1 < args.size()) {
|
|
max_iter = atoi(args[++argidx].c_str());
|
|
continue;
|
|
}
|
|
if (args[argidx] == "-D" && argidx+1 < args.size()) {
|
|
verilog_frontend += " -D " + args[++argidx];
|
|
continue;
|
|
}
|
|
if (args[argidx] == "-I" && argidx+1 < args.size()) {
|
|
verilog_frontend += " -I " + args[++argidx];
|
|
continue;
|
|
}
|
|
break;
|
|
}
|
|
extra_args(args, argidx, design);
|
|
|
|
TechmapWorker worker;
|
|
simplemap_get_mappers(worker.simplemap_mappers);
|
|
|
|
RTLIL::Design *map = new RTLIL::Design;
|
|
if (map_files.empty()) {
|
|
FILE *f = fmemopen(stdcells_code, strlen(stdcells_code), "rt");
|
|
Frontend::frontend_call(map, f, "<stdcells.v>", verilog_frontend);
|
|
fclose(f);
|
|
} else
|
|
for (auto &fn : map_files) {
|
|
FILE *f = fopen(fn.c_str(), "rt");
|
|
if (f == NULL)
|
|
log_cmd_error("Can't open map file `%s'\n", fn.c_str());
|
|
Frontend::frontend_call(map, f, fn, (fn.size() > 3 && fn.substr(fn.size()-3) == ".il") ? "ilang" : verilog_frontend);
|
|
fclose(f);
|
|
}
|
|
|
|
std::map<RTLIL::IdString, RTLIL::Module*> modules_new;
|
|
for (auto &it : map->modules_) {
|
|
if (it.first.substr(0, 2) == "\\$")
|
|
it.second->name = it.first.substr(1);
|
|
modules_new[it.second->name] = it.second;
|
|
}
|
|
map->modules_.swap(modules_new);
|
|
|
|
std::map<RTLIL::IdString, std::set<RTLIL::IdString>> celltypeMap;
|
|
for (auto &it : map->modules_) {
|
|
if (it.second->attributes.count("\\techmap_celltype") && !it.second->attributes.at("\\techmap_celltype").bits.empty()) {
|
|
char *p = strdup(it.second->attributes.at("\\techmap_celltype").decode_string().c_str());
|
|
for (char *q = strtok(p, " \t\r\n"); q; q = strtok(NULL, " \t\r\n"))
|
|
celltypeMap[RTLIL::escape_id(q)].insert(it.first);
|
|
free(p);
|
|
} else
|
|
celltypeMap[it.first].insert(it.first);
|
|
}
|
|
|
|
bool did_something = true;
|
|
std::set<RTLIL::Cell*> handled_cells;
|
|
while (did_something) {
|
|
did_something = false;
|
|
for (auto &mod_it : design->modules_)
|
|
if (worker.techmap_module(design, mod_it.second, map, handled_cells, celltypeMap, false))
|
|
did_something = true;
|
|
if (did_something)
|
|
design->check();
|
|
if (max_iter > 0 && --max_iter == 0)
|
|
break;
|
|
}
|
|
|
|
log("No more expansions possible.\n");
|
|
delete map;
|
|
|
|
log_pop();
|
|
}
|
|
} TechmapPass;
|
|
|
|
struct FlattenPass : public Pass {
|
|
FlattenPass() : Pass("flatten", "flatten design") { }
|
|
virtual void help()
|
|
{
|
|
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
|
|
log("\n");
|
|
log(" flatten [selection]\n");
|
|
log("\n");
|
|
log("This pass flattens the design by replacing cells by their implementation. This\n");
|
|
log("pass is very simmilar to the 'techmap' pass. The only difference is that this\n");
|
|
log("pass is using the current design as mapping library.\n");
|
|
log("\n");
|
|
}
|
|
virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
|
|
{
|
|
log_header("Executing FLATTEN pass (flatten design).\n");
|
|
log_push();
|
|
|
|
extra_args(args, 1, design);
|
|
|
|
TechmapWorker worker;
|
|
|
|
std::map<RTLIL::IdString, std::set<RTLIL::IdString>> celltypeMap;
|
|
for (auto &it : design->modules_)
|
|
celltypeMap[it.first].insert(it.first);
|
|
|
|
RTLIL::Module *top_mod = NULL;
|
|
if (design->full_selection())
|
|
for (auto &mod_it : design->modules_)
|
|
if (mod_it.second->get_bool_attribute("\\top"))
|
|
top_mod = mod_it.second;
|
|
|
|
bool did_something = true;
|
|
std::set<RTLIL::Cell*> handled_cells;
|
|
while (did_something) {
|
|
did_something = false;
|
|
if (top_mod != NULL) {
|
|
if (worker.techmap_module(design, top_mod, design, handled_cells, celltypeMap, true))
|
|
did_something = true;
|
|
} else {
|
|
for (auto &mod_it : design->modules_)
|
|
if (worker.techmap_module(design, mod_it.second, design, handled_cells, celltypeMap, true))
|
|
did_something = true;
|
|
}
|
|
}
|
|
|
|
log("No more expansions possible.\n");
|
|
|
|
if (top_mod != NULL) {
|
|
std::map<RTLIL::IdString, RTLIL::Module*> new_modules;
|
|
for (auto &mod_it : design->modules_)
|
|
if (mod_it.second == top_mod || mod_it.second->get_bool_attribute("\\blackbox")) {
|
|
new_modules[mod_it.first] = mod_it.second;
|
|
} else {
|
|
log("Deleting now unused module %s.\n", RTLIL::id2cstr(mod_it.first));
|
|
delete mod_it.second;
|
|
}
|
|
design->modules_.swap(new_modules);
|
|
}
|
|
|
|
log_pop();
|
|
}
|
|
} FlattenPass;
|
|
|