yosys/frontends
whitequark 66d0ed2bcc ast/simplify: don't bitblast async ROMs declared as `logic`.
Fixes #2020.
2020-05-05 04:16:59 +00:00
..
aiger aiger: fixes for ports that have start_offset != 0 2020-05-02 10:00:32 -07:00
ast ast/simplify: don't bitblast async ROMs declared as `logic`. 2020-05-05 04:16:59 +00:00
blif kernel: big fat patch to use more ID::*, otherwise ID(*) 2020-04-02 09:51:32 -07:00
ilang ilang, ast: Store parameter order and default value information. 2020-04-21 19:09:00 +02:00
json Update JSON front-end to process new attr/param encoding 2019-08-01 12:48:22 +02:00
liberty kernel: big fat patch to use more ID::*, otherwise ID(*) 2020-04-02 09:51:32 -07:00
rpc Add WASI platform support. 2020-04-30 18:56:25 +00:00
verific verific: ignore anonymous enums 2020-04-30 07:48:47 -07:00
verilog Set Verilog source location for explicit blocks (`begin` ... `end`). 2020-04-17 06:23:03 +00:00