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yosys/frontends/verilog
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Clifford Wolf fad8558eb5 Merged OSX fixes from Siesh1oo with some modifications 2014-03-13 12:48:10 +01:00
..
.gitignore added .gitignore files 2013-01-05 11:19:11 +01:00
Makefile.inc Various improvements in support for generate statements 2013-12-04 21:06:54 +01:00
const2ast.cc Fixed handling of unsized constants in verilog frontend 2014-01-24 15:05:24 +01:00
lexer.l Added support for `line compiler directive 2014-03-11 14:06:57 +01:00
parser.y Added Verilog support for "`default_nettype none" 2014-02-17 14:28:52 +01:00
preproc.cc Added Verilog support for "`default_nettype none" 2014-02-17 14:28:52 +01:00
verilog_frontend.cc Merged OSX fixes from Siesh1oo with some modifications 2014-03-13 12:48:10 +01:00
verilog_frontend.h Added Verilog support for "`default_nettype none" 2014-02-17 14:28:52 +01:00