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yosys/techlibs/gowin
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Clifford Wolf e9d73d2ee0 Indenting fixes in gowin sim cell lib 2016-11-08 18:54:00 +01:00
..
Makefile.inc Added initial version of "synth_gowin" 2016-11-01 11:31:13 +01:00
cells_map.v Added initial version of "synth_gowin" 2016-11-01 11:31:13 +01:00
cells_sim.v Indenting fixes in gowin sim cell lib 2016-11-08 18:54:00 +01:00
synth_gowin.cc Added hex constant support to write_verilog 2016-11-03 12:13:23 +01:00