mirror of https://github.com/YosysHQ/yosys.git
edd8ff2c07
The $div and $mod cells use truncating division semantics (rounding towards 0), as defined by e.g. Verilog. Another rounding mode, flooring (rounding towards negative infinity), can be used in e.g. VHDL. The new $divfloor cell provides this flooring division. This commit also fixes the handling of $div in opt_expr, which was previously optimized as if it was $divfloor. |
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| .. | ||
| Makefile.inc | ||
| muxpack.cc | ||
| opt.cc | ||
| opt_clean.cc | ||
| opt_demorgan.cc | ||
| opt_expr.cc | ||
| opt_lut.cc | ||
| opt_lut_ins.cc | ||
| opt_mem.cc | ||
| opt_merge.cc | ||
| opt_muxtree.cc | ||
| opt_reduce.cc | ||
| opt_rmdff.cc | ||
| opt_share.cc | ||
| pmux2shiftx.cc | ||
| rmports.cc | ||
| share.cc | ||
| wreduce.cc | ||