Clifford Wolf 7a99349de4 Improvements and bugfixes for generate blocks with local signals		2013-03-26 11:31:34 +01:00
..
Makefile.inc	initial import	2013-01-05 11:13:26 +01:00
ast.cc	Added mem2reg option to verilog frontend	2013-03-24 11:13:32 +01:00
ast.h	Added nosync attribute and some async reset related fixes	2013-03-25 17:13:14 +01:00
genrtlil.cc	Fixed handling of unconditional generate blocks	2013-03-26 09:44:54 +01:00
simplify.cc	Improvements and bugfixes for generate blocks with local signals	2013-03-26 11:31:34 +01:00