Clifford Wolf f483dce7c2 Added $eq/$neq -> $logic_not/$reduce_bool optimization		2015-04-29 07:28:15 +02:00
..
Makefile.inc	Fixed build with SMALL=1	2014-12-30 11:41:24 +01:00
opt.cc	Some cleanups in "clean"	2015-02-24 22:31:30 +01:00
opt_clean.cc	Added non-std verilog assume() statement	2015-02-26 18:47:39 +01:00
opt_const.cc	Added $eq/$neq -> $logic_not/$reduce_bool optimization	2015-04-29 07:28:15 +02:00
opt_muxtree.cc	Using design->selected_modules() in opt_*	2015-02-03 23:45:01 +01:00
opt_reduce.cc	Using design->selected_modules() in opt_*	2015-02-03 23:45:01 +01:00
opt_rmdff.cc	Improved handling of init values in opt_rmdff	2015-04-18 08:04:31 +02:00
opt_share.cc	Using design->selected_modules() in opt_*	2015-02-03 23:45:01 +01:00
share.cc	Replaced ezDefaultSAT with ezSatPtr	2015-02-21 12:15:41 +01:00
wreduce.cc	Added handling of bool-output cells to "wreduce"	2015-04-13 19:27:49 +02:00