yosys/frontends/verilog
Marcelina Kościelnicka a651204efa Fix handling of unique/unique0/priority cases in the frontend.
Basically:

- priority converts to (* full_case *)
- unique0 converts to (* parallel_case *)
- unique converts to (* parallel_case, full_case *)

Fixes #2596.
2021-02-25 21:53:58 +01:00
..
.gitignore Add "make coverage" 2018-08-27 14:22:21 +02:00
Makefile.inc Treat all bison warnings as errors in verilog front-end 2020-07-15 11:57:31 +02:00
const2ast.cc Replacing log_error for log_file_error due consistency 2020-03-31 12:01:29 -06:00
preproc.cc verilog: error on macro invocations with missing argument lists 2021-02-19 09:18:41 -05:00
preproc.h Add support for SystemVerilog-style `define to Verilog frontend 2020-03-27 16:08:26 +00:00
verilog_frontend.cc Fix SYNTHESIS always being defined in Verilog frontend 2020-12-01 01:37:19 +00:00
verilog_frontend.h frontend: cleanup to use more ID::*, more dict<> instead of map<> 2020-05-04 10:48:37 -07:00
verilog_lexer.l Fix handling of unique/unique0/priority cases in the frontend. 2021-02-25 21:53:58 +01:00
verilog_parser.y Fix handling of unique/unique0/priority cases in the frontend. 2021-02-25 21:53:58 +01:00