yosys/passes
Eddie Hung 1482f32d53
Merge pull request #1585 from YosysHQ/eddie/fix_abc9_lut
Interpret "abc9 -lut" as lut string only if [0-9:]
2019-12-20 13:09:00 -08:00
..
cmds use extra_args 2019-12-18 12:30:30 +01:00
equiv xilinx: Add xilinx_dffopt pass (#1557) 2019-12-18 13:43:43 +01:00
fsm Update fsm_detect bugfix 2019-11-12 17:31:30 +01:00
hierarchy Adopt @cliffordwolf's suggestion 2019-09-03 12:18:50 -07:00
memory Cleanup 2019-12-17 00:25:08 -08:00
opt Fix opt_expr.eqneq.cmpzero debug print 2019-12-15 20:40:38 +01:00
pmgen ice40_wrapcarry -unwrap to preserve 'src' attribute 2019-12-09 14:28:54 -08:00
proc proc_dlatch: Add error handling for incorrect always_(ff|latch|comb) usage 2019-11-21 20:46:41 +00:00
sat Fix sim for assignments with lhs<rhs size, fixes #1565 2019-12-17 17:36:30 +01:00
techmap Interpret "abc9 -lut" as lut string only if [0-9:] 2019-12-18 12:21:12 -08:00
tests Document (* gentb_skip *) attr for test_autotb 2019-09-18 12:41:35 -07:00