yosys/techlibs
Clifford Wolf dcdd5c11b4 Updated simlib to new $mem/$memwr interface 2014-07-16 11:46:40 +02:00
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cmos Added test comments to techlibs/cmos/cmos_cells.lib 2014-01-29 10:51:02 +01:00
common Updated simlib to new $mem/$memwr interface 2014-07-16 11:46:40 +02:00
xilinx Added "techmap -share_map" option 2013-11-24 19:50:25 +01:00
.gitignore added .gitignore files 2013-01-05 11:19:11 +01:00