mirror of https://github.com/YosysHQ/yosys.git
13 lines
560 B
Bash
13 lines
560 B
Bash
#!/bin/bash
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set -ex
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sed 's/DSP48E1/DSP48E1_UUT/; /DSP48E1_UUT/,/endmodule/ p; d;' < ../cells_sim.v > test_dsp_model_uut.v
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if [ ! -f "test_dsp_model_ref.v" ]; then
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cat /opt/Xilinx/Vivado/2019.1/data/verilog/src/unisims/DSP48E1.v > test_dsp_model_ref.v
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fi
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for tb in mult_allreg_nopreadd_nocasc mult_noreg_nopreadd_nocasc \
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mult_allreg_preadd_nocasc mult_noreg_preadd_nocasc
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do
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iverilog -s $tb -s glbl -o test_dsp_model test_dsp_model.v test_dsp_model_uut.v test_dsp_model_ref.v /opt/Xilinx/Vivado/2019.1/data/verilog/src/glbl.v
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vvp -N ./test_dsp_model
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done
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