riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity
6,442 Commits 76 Branches 48 Tags 62 MiB
Commit Graph

3 Commits

Author SHA1 Message Date
David Shah d60b3c0dc8 DSP48E1 sim model: fix seq tests and add preadder tests 
Signed-off-by: David Shah <dave@ds0.me>
 2019-08-08 11:18:37 +01:00
David Shah e7dbe7bb3d DSP48E1 sim model: seq test working 
Signed-off-by: David Shah <dave@ds0.me>
 2019-08-08 10:52:04 +01:00
David Shah f0f352e971 [wip] sim model testing 
Signed-off-by: David Shah <dave@ds0.me>
 2019-08-08 10:05:11 +01:00