mirror of https://github.com/YosysHQ/yosys.git
26 lines
582 B
Verilog
26 lines
582 B
Verilog
// ---------------------------------------
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module \$__ABC_DPR16X4_COMB (input [3:0] A, S, output [3:0] Y);
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assign Y = A;
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endmodule
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module \$__ABC_DPR16X4_SEQ (
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input [3:0] DI,
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input [3:0] WAD,
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input WRE,
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input WCK,
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input [3:0] RAD,
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output [3:0] DO
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);
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parameter WCKMUX = "WCK";
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parameter WREMUX = "WRE";
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parameter [63:0] INITVAL = 64'h0000000000000000;
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TRELLIS_DPR16X4 #(
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.WCKMUX(WCKMUX), .WREMUX(WREMUX), .INITVAL(INITVAL)
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) _TECHMAP_REPLACE_ (
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.DI(DI), .WAD(WAD), .WRE(WRE), .WCK(WCK),
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.RAD(RAD), .DO(DO)
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);
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endmodule
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