| .. |
|
.gitignore
|
ecp5: First BRAM type maps successfully
|
2018-10-10 16:35:19 +01:00 |
|
Makefile.inc
|
ecp5 to use abc_map.v and _unmap.v
|
2019-08-20 18:59:03 -07:00 |
|
abc_5g.box
|
ecp5 to use abc_map.v and _unmap.v
|
2019-08-20 18:59:03 -07:00 |
|
abc_5g.lut
|
ecp5: Add abc9 option
|
2019-06-14 17:15:02 +01:00 |
|
abc_5g_nowide.lut
|
Add _nowide variants of LUT libraries in -nowidelut flows
|
2019-06-26 10:23:29 -07:00 |
|
abc_map.v
|
ecp5 to use abc_map.v and _unmap.v
|
2019-08-20 18:59:03 -07:00 |
|
abc_model.v
|
ecp5 to use abc_map.v and _unmap.v
|
2019-08-20 18:59:03 -07:00 |
|
abc_unmap.v
|
ecp5 to use abc_map.v and _unmap.v
|
2019-08-20 18:59:03 -07:00 |
|
arith_map.v
|
ecp5: Improve mapping of $alu when BI is used
|
2019-06-21 09:45:11 +01:00 |
|
bram.txt
|
ecp5: First BRAM type maps successfully
|
2018-10-10 16:35:19 +01:00 |
|
brams_connect.py
|
ecp5: Script for BRAM IO connections
|
2018-10-10 16:11:00 +01:00 |
|
brams_init.py
|
ecp5: First BRAM type maps successfully
|
2018-10-10 16:35:19 +01:00 |
|
brams_map.v
|
ecp5: Disable LSR inversion
|
2018-10-16 12:48:39 +01:00 |
|
cells_bb.v
|
ecp5: Add DDRDLLA
|
2019-02-19 19:34:37 +00:00 |
|
cells_map.v
|
Merge origin/master
|
2019-06-27 11:20:15 -07:00 |
|
cells_sim.v
|
ecp5 to use abc_map.v and _unmap.v
|
2019-08-20 18:59:03 -07:00 |
|
ecp5_ffinit.cc
|
ecp5: Demote conflicting FF init values to a warning
|
2019-03-04 11:26:20 +00:00 |
|
latches_map.v
|
ecp5: Add latch inference
|
2018-10-19 15:16:40 +01:00 |
|
lutram.txt
|
synth_ecp5: rename dram to lutram everywhere.
|
2019-07-16 20:45:12 +00:00 |
|
lutrams_map.v
|
synth_ecp5: rename dram to lutram everywhere.
|
2019-07-16 20:45:12 +00:00 |
|
synth_ecp5.cc
|
ecp5 to use abc_map.v and _unmap.v
|
2019-08-20 18:59:03 -07:00 |
55acf3120f