mirror of https://github.com/YosysHQ/yosys.git
5157691f0e
This results in further massive gains in performance, modest decrease in compile time, and, for designs without feedback arcs, makes it possible to run eval() once per clock edge in certain conditions. |
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aiger | ||
blif | ||
btor | ||
cxxrtl | ||
edif | ||
firrtl | ||
ilang | ||
intersynth | ||
json | ||
protobuf | ||
simplec | ||
smt2 | ||
smv | ||
spice | ||
table | ||
verilog |