mirror of https://github.com/YosysHQ/yosys.git
4fef9689ab
In some cases the memory_bram pass shuffles the order of the bits in a memory's RD_DATA port. Although the order of the bits in the WR_DATA and WR_EN ports is changed to match the RD_DATA port, the order of the bits in the initialization data is not. This causes reads of initialized memories to return invalid data (until the initialization data is overwritten). This commit fixes the bug by shuffling the initdata bits in exactly the same order as the RD_DATA/WR_DATA/WR_EN bits. |
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| cmds | ||
| equiv | ||
| fsm | ||
| hierarchy | ||
| memory | ||
| opt | ||
| proc | ||
| sat | ||
| techmap | ||
| tests | ||