Clifford Wolf 3fa374a698 Add fminit pass ... Signed-off-by: Clifford Wolf <clifford@clifford.at>		2020-01-09 21:22:54 +01:00
..
Makefile.inc	Add fminit pass	2020-01-09 21:22:54 +01:00
assertpmux.cc	Fixed the help summary line for a few commands	2019-06-19 15:27:04 -04:00
async2sync.cc	Fix $dlatch handling in async2sync	2019-09-30 14:58:23 +02:00
clk2fflogic.cc	Fix tests/various/async FFL test	2019-07-09 22:44:39 +02:00
cutpoint.cc	Fixed the help summary line for a few commands	2019-06-19 15:27:04 -04:00
eval.cc	Use State::S{0,1}	2019-08-06 16:22:47 -07:00
example.v	Added support for shifter cells to SAT generator	2013-06-08 15:12:08 +02:00
example.ys	Fixes in old SAT example.ys	2014-09-01 11:45:47 +02:00
expose.cc	More use of IdString::in()	2019-08-15 09:23:57 -07:00
fmcombine.cc	Fix typo in fmcombine log message, fixes #1063	2019-06-05 09:26:44 +02:00
fminit.cc	Add fminit pass	2020-01-09 21:22:54 +01:00
freduce.cc	stoi -> atoi	2019-08-07 11:09:17 -07:00
miter.cc	substr() -> compare()	2019-08-07 12:20:08 -07:00
mutate.cc	stoi -> atoi	2019-08-07 11:09:17 -07:00
sat.cc	Revert "Be mindful that sigmap(wire) could have dupes when checking \init"	2019-10-08 12:41:24 -07:00
sim.cc	Fix sim for assignments with lhs<rhs size, fixes #1565	2019-12-17 17:36:30 +01:00
supercover.cc	Improvements in "supercover" pass	2019-02-27 11:45:13 -08:00