yosys/frontends/verilog
Clifford Wolf 482d9208aa Added read_verilog -sv options, added support for bit, logic,
allways_ff, always_comb, and always_latch
2014-06-12 11:54:20 +02:00
..
.gitignore added .gitignore files 2013-01-05 11:19:11 +01:00
Makefile.inc Various improvements in support for generate statements 2013-12-04 21:06:54 +01:00
const2ast.cc Fixed handling of unsized constants in verilog frontend 2014-01-24 15:05:24 +01:00
lexer.l Added read_verilog -sv options, added support for bit, logic, 2014-06-12 11:54:20 +02:00
parser.y Added read_verilog -sv options, added support for bit, logic, 2014-06-12 11:54:20 +02:00
preproc.cc Added Verilog support for "`default_nettype none" 2014-02-17 14:28:52 +01:00
verilog_frontend.cc Added read_verilog -sv options, added support for bit, logic, 2014-06-12 11:54:20 +02:00
verilog_frontend.h Added read_verilog -sv options, added support for bit, logic, 2014-06-12 11:54:20 +02:00