yosys/techlibs
Eddie Hung 480a04cb3c Realistic delays for RAM32X1D too 2019-06-25 09:34:28 -07:00
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achronix Reduce amount of trailing whitespace in code base 2019-02-28 14:58:11 -08:00
anlogic Reduce amount of trailing whitespace in code base 2019-02-28 14:58:11 -08:00
common Make doc consistent 2019-06-14 10:32:46 -07:00
coolrunner2 Unify usage of noflatten among architectures 2019-01-04 11:37:25 +01:00
easic Fix typographical and grammatical errors and inconsistencies. 2019-01-02 13:12:17 +00:00
ecp5 Re-enable dist RAM boxes for ECP5 2019-06-24 22:12:50 -07:00
gowin Merge branch 'master' of https://github.com/dh73/yosys_gowin into dh73-master 2019-04-22 09:09:27 +02:00
greenpak4 techlibs/greenpak4/cells_map.v: Harmonize whitespace within lut module 2019-02-26 09:40:46 -08:00
ice40 Fix and cleanup ice40 boxes for carry in/out 2019-06-22 14:27:41 -07:00
intel Fix formatting for synth_intel.cc 2019-05-09 08:40:05 -07:00
sf2 Add link to SF2 / igloo2 macro library guide 2019-03-07 09:08:26 -08:00
xilinx Realistic delays for RAM32X1D too 2019-06-25 09:34:28 -07:00
.gitignore added .gitignore files 2013-01-05 11:19:11 +01:00