mirror of https://github.com/YosysHQ/yosys.git
5b779f7f4e
By instantiating the LUTRAM cell directly, we avoid a trip through altsyncram, which speeds up Quartus synthesis time. This also gives a little more flexibility, as Yosys can build RAMs out of individual 32x1 LUTRAM cells. While working on this, I discovered that the mem_init0 parameter of <family>_mlab_cell gets ignored by Quartus. |
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| .. | ||
| add_sub.ys | ||
| adffs.ys | ||
| counter.ys | ||
| dffs.ys | ||
| fsm.ys | ||
| logic.ys | ||
| lutram.ys | ||
| mux.ys | ||
| quartus_ice.ys | ||
| run-test.sh | ||
| shifter.ys | ||
| tribuf.ys | ||