yosys/frontends
Clifford Wolf 638be461c3 Fix mem2reg handling of memories with upto data ports, fixes #888
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-03-21 22:21:17 +01:00
..
aiger Add author name 2019-03-19 08:52:06 -07:00
ast Fix mem2reg handling of memories with upto data ports, fixes #888 2019-03-21 22:21:17 +01:00
blif Add missing "[options]" to read_blif help 2019-02-08 12:41:39 -08:00
ilang Add "read_ilang -[no]overwrite" 2018-12-23 15:45:09 +01:00
json Consistent use of 'override' for virtual methods in derived classes. 2018-07-20 23:51:06 -07:00
liberty Fix typographical and grammatical errors and inconsistencies. 2019-01-02 13:12:17 +00:00
verific Merge pull request #858 from YosysHQ/clifford/svalabels 2019-03-09 11:14:57 -08:00
verilog Improve read_verilog debug output capabilities 2019-03-21 20:52:29 +01:00