mirror of https://github.com/YosysHQ/yosys.git
9f0892159e
For connection `assign a = b;`, `sigmap(a)` returns `b`. This is
exactly the opposite of the desired canonicalization for driven bits.
Consider the following code:
module foo(inout a, b);
assign a = b;
endmodule
module bar(output c);
foo f(c, 1'b0);
endmodule
Before this commit, the inout ports would be swapped after flattening
(and cause a crash while attempting to drive a constant value).
This issue was introduced in
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| .. | ||
| .gitignore | ||
| abc9.ys | ||
| aigmap.ys | ||
| autopurge.ys | ||
| bug2183.ys | ||
| bug2321.ys | ||
| bug2332.ys | ||
| cellname.ys | ||
| clkbufmap.ys | ||
| cmp2lcu.ys | ||
| dffinit.ys | ||
| dfflegalize_adff.ys | ||
| dfflegalize_adff_init.ys | ||
| dfflegalize_adlatch.ys | ||
| dfflegalize_adlatch_init.ys | ||
| dfflegalize_dff.ys | ||
| dfflegalize_dff_init.ys | ||
| dfflegalize_dffsr.ys | ||
| dfflegalize_dffsr_init.ys | ||
| dfflegalize_dlatch.ys | ||
| dfflegalize_dlatch_const.ys | ||
| dfflegalize_dlatch_init.ys | ||
| dfflegalize_dlatchsr.ys | ||
| dfflegalize_dlatchsr_init.ys | ||
| dfflegalize_inv.ys | ||
| dfflegalize_mince.ys | ||
| dfflegalize_minsrst.ys | ||
| dfflegalize_sr.ys | ||
| dfflegalize_sr_init.ys | ||
| dfflibmap-sim.v | ||
| dfflibmap.lib | ||
| dfflibmap.ys | ||
| dffunmap.ys | ||
| extractinv.ys | ||
| iopadmap.ys | ||
| mem_simple_4x1_cells.v | ||
| mem_simple_4x1_map.v | ||
| mem_simple_4x1_runtest.sh | ||
| mem_simple_4x1_tb.v | ||
| mem_simple_4x1_uut.v | ||
| recursive.v | ||
| recursive_map.v | ||
| recursive_runtest.sh | ||
| run-test.sh | ||
| shiftx2mux.ys | ||
| techmap_replace.ys | ||
| wireinit.ys | ||
| zinit.ys | ||