yosys/frontends
whitequark deff6a9546
Merge pull request #2501 from zachjs/genrtlil-tern-sign
genrtlil: fix mux2rtlil generated wire signedness
2020-12-23 23:15:56 +00:00
..
aiger Remove YS_ATTRIBUTE(unused) where present just for log_assert()/log_debug(). 2020-06-19 15:48:58 +00:00
ast Merge pull request #2501 from zachjs/genrtlil-tern-sign 2020-12-23 23:15:56 +00:00
blif Use C++11 final/override keywords. 2020-06-18 23:34:52 +00:00
json Use C++11 final/override keywords. 2020-06-18 23:34:52 +00:00
liberty Use C++11 final/override keywords. 2020-06-18 23:34:52 +00:00
rpc Fix argument handling in connect_rpc 2020-10-19 13:40:57 +02:00
rtlil rtlil: remove dotted identifiers. 2020-11-25 16:47:20 +00:00
verific Bump required Verific version 2020-12-02 15:18:04 +01:00
verilog Fix SYNTHESIS always being defined in Verilog frontend 2020-12-01 01:37:19 +00:00