yosys/frontends
Clifford Wolf 26c4323d48
Merge pull request #479 from Fatsie/latch_without_data
Some standard cell libraries include a latch with only set/reset.
2018-01-05 23:00:28 +01:00
..
ast Bugfix in hierarchy handling of blackbox module ports 2018-01-05 13:28:45 +01:00
blif Increase maximum LUT size in blifparse to 12 bits 2017-09-27 15:27:42 +02:00
ilang Added avail params to ilang format, check module params in 'hierarchy -check' 2016-10-22 11:05:49 +02:00
json Parse reals as string in JSON front-end 2017-09-26 14:37:03 +02:00
liberty Some standard cell libraries include a latch with only set/reset. 2018-01-03 21:36:02 +00:00
verific Add support for Verific PRIM_SVA_NOT properties 2017-12-10 01:10:03 +01:00
verilog Bugfix in verilog_defaults argument parser 2017-12-24 17:21:37 +01:00