yosys/passes
Clifford Wolf 404bcc2d1e Fixed dfflibmap endless-loop bug 2013-12-20 12:13:51 +01:00
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abc Tighter integration of ABC build 2013-11-27 09:08:35 +01:00
cmds Replaced RTLIL::Const::str with generic decoder method 2013-12-04 14:14:05 +01:00
extract Automatically run "proc" on extract map files 2013-07-24 20:19:08 +02:00
fsm Fixes in fsm detect/extract for better detection of non-fsm circuits 2013-12-06 12:53:20 +01:00
hierarchy Replaced signed_parameters API with CONST_FLAG_SIGNED 2013-12-04 14:24:44 +01:00
memory Replaced RTLIL::Const::str with generic decoder method 2013-12-04 14:14:05 +01:00
opt Cleanups and bugfixes in response to new internal cell checker 2013-11-11 00:39:45 +01:00
proc Major improvements in mem2reg and added "init" sync rules 2013-11-21 13:49:00 +01:00
sat Added sat -max_undef feature 2013-12-07 23:58:55 +01:00
scc fixed typos 2013-03-18 07:28:31 +01:00
submod Replaced RTLIL::Const::str with generic decoder method 2013-12-04 14:14:05 +01:00
techmap Fixed dfflibmap endless-loop bug 2013-12-20 12:13:51 +01:00