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yosys/tests/fmt
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Catherine 62bbd086b1 cxxrtl: reorganize runtime component files. 
In preparation for substantial expansion of CXXRTL's runtime, this commit
reorganizes the files used by the implementation. Only minimal changes are
required in a consumer.

First, change:
  -I$(yosys-config --datdir)/include
to:
  -I$(yosys-config --datdir)/include/backends/cxxrtl/runtime

Second, change:
  #include <backends/cxxrtl/cxxrtl.h>
to:
  #include <cxxrtl/cxxrtl.h>
(and do the same for cxxrtl_vcd.h, etc.)
 		2023-11-28 15:32:36 +00:00
..
fuzz fmt: merge fuzzers since we don't rely on BigInteger logic 2023-08-11 04:46:52 +02:00
.gitignore fmt: add tests for Verilog round trip of format expressions. 2023-08-11 04:46:52 +02:00
always_comb.v cxxrtl: WIP: adjust comb display cells to only fire on change 2023-08-11 04:46:52 +02:00
always_comb_tb.cc cxxrtl: include iostream when prints are used 2023-08-17 07:08:22 +02:00
always_comb_tb.v cxxrtl: store comb $print cell last EN/ARGS in module 2023-08-11 04:46:52 +02:00
always_display.v fmt: add tests for Verilog round trip of format expressions. 2023-08-11 04:46:52 +02:00
always_full.v verilog_backend: emit sync `$print` cells with same triggers together 2023-08-11 04:46:52 +02:00
always_full_tb.cc cxxrtl: include iostream when prints are used 2023-08-17 07:08:22 +02:00
always_full_tb.v verilog_backend: emit sync `$print` cells with same triggers together 2023-08-11 04:46:52 +02:00
display_lm.v fmt: rudimentary %m support (= %l) 2023-08-11 04:46:52 +02:00
display_lm_tb.cc cxxrtl: include iostream when prints are used 2023-08-17 07:08:22 +02:00
initial_display.v fmt: format %t consistently at initial 2023-08-11 04:46:52 +02:00
roundtrip.v fmt: add tests for Verilog round trip of format expressions. 2023-08-11 04:46:52 +02:00
roundtrip_tb.v fmt: add tests for Verilog round trip of format expressions. 2023-08-11 04:46:52 +02:00
run-test.sh cxxrtl: reorganize runtime component files. 2023-11-28 15:32:36 +00:00