Clifford Wolf 653750faac Small bugfixes in freduce pass		2013-08-06 15:53:09 +02:00
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abc	Added $lut cells and abc lut mapping support	2013-07-23 16:19:34 +02:00
cmds	Added "design" command (-reset, -save, -load)	2013-07-27 14:27:51 +02:00
dfflibmap	Added yosys-svgviewer to build system and renamed filterlib to yosys-filterlib	2013-03-27 10:51:15 +01:00
extract	Automatically run "proc" on extract map files	2013-07-24 20:19:08 +02:00
fsm	Renamed opt_rmunused to opt_clean	2013-06-05 07:07:31 +02:00
hierarchy	Improved log messages generated by hierarchy pass	2013-05-26 12:20:51 +02:00
memory	Added -nomap option to memory pass	2013-03-21 09:11:06 +01:00
opt	Bugfixes for empty signal vectors	2013-07-10 12:52:29 +02:00
proc	Added nosync attribute and some async reset related fixes	2013-03-25 17:13:14 +01:00
sat	Small bugfixes in freduce pass	2013-08-06 15:53:09 +02:00
scc	fixed typos	2013-03-18 07:28:31 +01:00
submod	Renamed opt_rmunused to opt_clean	2013-06-05 07:07:31 +02:00
techmap	Fixed techmap/flatten for positional module arguments	2013-05-26 12:21:17 +02:00