riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity
yosys/tests/arch/intel_alm
History
Claire Wolf 7112f187cd Add missing .gitignore file 
Signed-off-by: Claire Wolf <claire@symbioticeda.com>
 		2020-06-04 22:25:47 +02:00
..
.gitignore Add missing .gitignore file 2020-06-04 22:25:47 +02:00
add_sub.ys synth_intel_alm: alternative synthesis for Intel FPGAs 2020-04-15 11:40:41 +02:00
adffs.ys synth_intel_alm: alternative synthesis for Intel FPGAs 2020-04-15 11:40:41 +02:00
counter.ys synth_intel_alm: alternative synthesis for Intel FPGAs 2020-04-15 11:40:41 +02:00
dffs.ys synth_intel_alm: alternative synthesis for Intel FPGAs 2020-04-15 11:40:41 +02:00
fsm.ys synth_intel_alm: alternative synthesis for Intel FPGAs 2020-04-15 11:40:41 +02:00
logic.ys synth_intel_alm: alternative synthesis for Intel FPGAs 2020-04-15 11:40:41 +02:00
lutram.ys intel_alm: direct LUTRAM cell instantiation 2020-05-07 21:03:13 +02:00
mux.ys synth_intel_alm: alternative synthesis for Intel FPGAs 2020-04-15 11:40:41 +02:00
quartus_ice.ys intel_alm: work around a Quartus ICE 2020-04-23 11:03:28 +02:00
run-test.sh synth_intel_alm: alternative synthesis for Intel FPGAs 2020-04-15 11:40:41 +02:00
shifter.ys synth_intel_alm: alternative synthesis for Intel FPGAs 2020-04-15 11:40:41 +02:00
tribuf.ys synth_intel_alm: alternative synthesis for Intel FPGAs 2020-04-15 11:40:41 +02:00