mirror of https://github.com/YosysHQ/yosys.git
351 lines
10 KiB
C++
351 lines
10 KiB
C++
/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/yosys.h"
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#include "kernel/sigtools.h"
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#include "kernel/modtools.h"
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USING_YOSYS_NAMESPACE
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using namespace RTLIL;
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PRIVATE_NAMESPACE_BEGIN
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struct WreduceConfig
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{
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std::set<IdString> supported_cell_types;
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WreduceConfig()
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{
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supported_cell_types = {
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"$not", "$pos", "$neg",
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"$and", "$or", "$xor", "$xnor",
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"$shl", "$shr", "$sshl", "$sshr", "$shift", "$shiftx",
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"$lt", "$le", "$eq", "$ne", "$eqx", "$nex", "$ge", "$gt",
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"$add", "$sub", // "$mul", "$div", "$mod", "$pow",
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"$mux", "$pmux"
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};
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}
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};
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struct WreduceWorker
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{
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WreduceConfig *config;
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Module *module;
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ModIndex mi;
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std::set<Cell*, IdString::compare_ptr_by_name<Cell>> work_queue_cells;
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std::set<SigBit> work_queue_bits;
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WreduceWorker(WreduceConfig *config, Module *module) :
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config(config), module(module), mi(module) { }
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void run_cell_mux(Cell *cell)
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{
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// Reduce size of MUX if inputs agree on a value for a bit or a output bit is unused
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SigSpec sig_a = mi.sigmap(cell->getPort("\\A"));
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SigSpec sig_b = mi.sigmap(cell->getPort("\\B"));
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SigSpec sig_s = mi.sigmap(cell->getPort("\\S"));
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SigSpec sig_y = mi.sigmap(cell->getPort("\\Y"));
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std::vector<SigBit> bits_removed;
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for (int i = SIZE(sig_y)-1; i >= 0; i--)
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{
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auto info = mi.query(sig_y[i]);
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if (!info->is_output && SIZE(info->ports) <= 1) {
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bits_removed.push_back(Sx);
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continue;
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}
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SigBit ref = sig_a[i];
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for (int k = 0; k < SIZE(sig_s); k++) {
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if (ref != Sx && sig_b[k*SIZE(sig_a) + i] != Sx && ref != sig_b[k*SIZE(sig_a) + i])
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goto no_match_ab;
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if (sig_b[k*SIZE(sig_a) + i] != Sx)
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ref = sig_b[k*SIZE(sig_a) + i];
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}
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if (0)
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no_match_ab:
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break;
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bits_removed.push_back(ref);
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}
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if (bits_removed.empty())
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return;
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SigSpec sig_removed;
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for (int i = SIZE(bits_removed)-1; i >= 0; i--)
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sig_removed.append_bit(bits_removed[i]);
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if (SIZE(bits_removed) == SIZE(sig_y)) {
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log("Removed cell %s.%s (%s).\n", log_id(module), log_id(cell), log_id(cell->type));
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module->connect(sig_y, sig_removed);
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module->remove(cell);
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return;
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}
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log("Removed top %d bits (of %d) from mux cell %s.%s (%s).\n",
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SIZE(sig_removed), SIZE(sig_y), log_id(module), log_id(cell), log_id(cell->type));
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int n_removed = SIZE(sig_removed);
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int n_kept = SIZE(sig_y) - SIZE(sig_removed);
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SigSpec new_work_queue_bits;
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new_work_queue_bits.append(sig_a.extract(n_kept, n_removed));
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new_work_queue_bits.append(sig_y.extract(n_kept, n_removed));
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SigSpec new_sig_a = sig_a.extract(0, n_kept);
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SigSpec new_sig_y = sig_y.extract(0, n_kept);
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SigSpec new_sig_b;
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for (int k = 0; k < SIZE(sig_s); k++) {
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new_sig_b.append(sig_b.extract(k*SIZE(sig_a), n_kept));
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new_work_queue_bits.append(sig_b.extract(k*SIZE(sig_a) + n_kept, n_removed));
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}
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for (auto bit : new_work_queue_bits)
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work_queue_bits.insert(bit);
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cell->setPort("\\A", new_sig_a);
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cell->setPort("\\B", new_sig_b);
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cell->setPort("\\Y", new_sig_y);
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cell->fixup_parameters();
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module->connect(sig_y.extract(n_kept, n_removed), sig_removed);
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}
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void run_reduce_inport(Cell *cell, char port, int max_port_size, bool &port_signed, bool &did_something)
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{
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port_signed = cell->getParam(stringf("\\%c_SIGNED", port)).as_bool();
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SigSpec sig = mi.sigmap(cell->getPort(stringf("\\%c", port)));
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if (port == 'B' && cell->type.in("$shl", "$shr", "$sshl", "$sshr"))
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port_signed = false;
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int bits_removed = 0;
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if (SIZE(sig) > max_port_size) {
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bits_removed = SIZE(sig) - max_port_size;
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for (auto bit : sig.extract(max_port_size, bits_removed))
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work_queue_bits.insert(bit);
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sig = sig.extract(0, max_port_size);
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}
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if (port_signed) {
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while (SIZE(sig) > 1 && sig[SIZE(sig)-1] == sig[SIZE(sig)-2])
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work_queue_bits.insert(sig[SIZE(sig)-1]), sig.remove(SIZE(sig)-1), bits_removed++;
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} else {
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while (SIZE(sig) > 1 && sig[SIZE(sig)-1] == S0)
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work_queue_bits.insert(sig[SIZE(sig)-1]), sig.remove(SIZE(sig)-1), bits_removed++;
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}
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if (bits_removed) {
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log("Removed top %d bits (of %d) from port %c of cell %s.%s (%s).\n",
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bits_removed, SIZE(sig) + bits_removed, port, log_id(module), log_id(cell), log_id(cell->type));
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cell->setPort(stringf("\\%c", port), sig);
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did_something = true;
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}
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}
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void run_cell(Cell *cell)
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{
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bool did_something = false;
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if (!cell->type.in(config->supported_cell_types))
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return;
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if (cell->type.in("$mux", "$pmux"))
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return run_cell_mux(cell);
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// Reduce size of ports A and B based on constant input bits and size of output port
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int max_port_a_size = cell->hasPort("\\A") ? SIZE(cell->getPort("\\A")) : -1;
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int max_port_b_size = cell->hasPort("\\B") ? SIZE(cell->getPort("\\B")) : -1;
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if (cell->type.in("$not", "$pos", "$neg", "$and", "$or", "$xor", "$add", "$sub")) {
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max_port_a_size = std::min(max_port_a_size, SIZE(cell->getPort("\\Y")));
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max_port_b_size = std::min(max_port_b_size, SIZE(cell->getPort("\\Y")));
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}
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bool port_a_signed = false;
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bool port_b_signed = false;
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if (max_port_a_size >= 0 && cell->type != "$shiftx")
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run_reduce_inport(cell, 'A', max_port_a_size, port_a_signed, did_something);
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if (max_port_b_size >= 0)
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run_reduce_inport(cell, 'B', max_port_b_size, port_b_signed, did_something);
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// Reduce size of port Y based on sizes for A and B and unused bits in Y
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SigSpec sig = mi.sigmap(cell->getPort("\\Y"));
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int bits_removed = 0;
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if (port_a_signed && cell->type == "$shr") {
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// do not reduce size of output on $shr cells with signed A inputs
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} else {
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while (SIZE(sig) > 0)
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{
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auto info = mi.query(sig[SIZE(sig)-1]);
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if (info->is_output || SIZE(info->ports) > 1)
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break;
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sig.remove(SIZE(sig)-1);
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bits_removed++;
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}
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}
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if (cell->type.in("$pos", "$add", "$mul", "$and", "$or", "$xor"))
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{
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bool is_signed = cell->getParam("\\A_SIGNED").as_bool();
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int a_size = 0, b_size = 0;
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if (cell->hasPort("\\A")) a_size = SIZE(cell->getPort("\\A"));
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if (cell->hasPort("\\B")) b_size = SIZE(cell->getPort("\\B"));
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int max_y_size = std::max(a_size, b_size);
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if (cell->type == "$add")
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max_y_size++;
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if (cell->type == "$mul")
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max_y_size = a_size + b_size;
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while (SIZE(sig) > 1 && SIZE(sig) > max_y_size) {
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module->connect(sig[SIZE(sig)-1], is_signed ? sig[SIZE(sig)-2] : S0);
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sig.remove(SIZE(sig)-1);
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bits_removed++;
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}
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}
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if (SIZE(sig) == 0) {
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log("Removed cell %s.%s (%s).\n", log_id(module), log_id(cell), log_id(cell->type));
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module->remove(cell);
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return;
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}
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if (bits_removed) {
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log("Removed top %d bits (of %d) from port Y of cell %s.%s (%s).\n",
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bits_removed, SIZE(sig) + bits_removed, log_id(module), log_id(cell), log_id(cell->type));
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cell->setPort("\\Y", sig);
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did_something = true;
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}
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if (did_something) {
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cell->fixup_parameters();
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run_cell(cell);
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}
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}
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static int count_nontrivial_wire_attrs(RTLIL::Wire *w)
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{
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int count = w->attributes.size();
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count -= w->attributes.count("\\src");
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count -= w->attributes.count("\\unused_bits");
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return count;
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}
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void run()
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{
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for (auto c : module->selected_cells())
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work_queue_cells.insert(c);
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while (!work_queue_cells.empty())
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{
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work_queue_bits.clear();
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for (auto c : work_queue_cells)
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run_cell(c);
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work_queue_cells.clear();
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for (auto bit : work_queue_bits)
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for (auto port : mi.query_ports(bit))
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if (module->selected(port.cell))
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work_queue_cells.insert(port.cell);
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}
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for (auto w : module->selected_wires())
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{
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int unused_top_bits = 0;
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if (w->port_id > 0 || count_nontrivial_wire_attrs(w) > 0)
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continue;
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for (int i = SIZE(w)-1; i >= 0; i--) {
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SigBit bit(w, i);
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auto info = mi.query(bit);
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if (info && (info->is_input || info->is_output || SIZE(info->ports) > 0))
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break;
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unused_top_bits++;
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}
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if (0 < unused_top_bits && unused_top_bits < SIZE(w)) {
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log("Removed top %d bits (of %d) from wire %s.%s.\n", unused_top_bits, SIZE(w), log_id(module), log_id(w));
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Wire *nw = module->addWire(NEW_ID, w);
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nw->width = SIZE(w) - unused_top_bits;
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module->connect(nw, SigSpec(w).extract(0, SIZE(nw)));
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module->swap_names(w, nw);
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}
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}
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}
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};
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struct WreducePass : public Pass {
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WreducePass() : Pass("wreduce", "reduce the word size of operations is possible") { }
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virtual void help()
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" wreduce [options] [selection]\n");
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log("\n");
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log("This command reduces the word size of operations. For example it will replace\n");
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log("the 32 bit adders in the following code with adders of more appropriate widths:\n");
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log("\n");
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log(" module test(input [3:0] a, b, c, output [7:0] y);\n");
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log(" assign y = a + b + c + 1;\n");
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log(" endmodule\n");
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log("\n");
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}
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virtual void execute(std::vector<std::string> args, Design *design)
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{
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WreduceConfig config;
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log_header("Executing WREDUCE pass (reducing word size of cells).\n");
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++) {
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break;
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}
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extra_args(args, argidx, design);
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for (auto module : design->selected_modules())
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{
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if (module->has_processes_warn())
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continue;
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WreduceWorker worker(&config, module);
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worker.run();
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}
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}
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} WreducePass;
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PRIVATE_NAMESPACE_END
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