mirror of https://github.com/YosysHQ/yosys.git
352 lines
11 KiB
C++
352 lines
11 KiB
C++
/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/register.h"
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#include "kernel/celltypes.h"
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#include "kernel/sigtools.h"
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#include "kernel/rtlil.h"
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#include "kernel/log.h"
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#include <tuple>
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struct SpliceWorker
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{
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RTLIL::Design *design;
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RTLIL::Module *module;
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bool sel_by_cell;
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bool sel_by_wire;
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bool sel_any_bit;
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bool no_outputs;
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std::set<RTLIL::IdString> ports;
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std::set<RTLIL::IdString> no_ports;
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CellTypes ct;
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SigMap sigmap;
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std::vector<RTLIL::SigBit> driven_bits;
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std::map<RTLIL::SigBit, int> driven_bits_map;
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std::set<RTLIL::SigSpec> driven_chunks;
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std::map<RTLIL::SigSpec, RTLIL::SigSpec> spliced_signals_cache;
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std::map<RTLIL::SigSpec, RTLIL::SigSpec> sliced_signals_cache;
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SpliceWorker(RTLIL::Design *design, RTLIL::Module *module) : design(design), module(module), ct(design), sigmap(module)
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{
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}
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RTLIL::SigSpec get_sliced_signal(RTLIL::SigSpec sig)
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{
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if (sig.size() == 0 || sig.is_fully_const())
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return sig;
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if (sliced_signals_cache.count(sig))
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return sliced_signals_cache.at(sig);
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int offset = 0;
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int p = driven_bits_map.at(sig.extract(0, 1).to_single_sigbit()) - 1;
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while (driven_bits.at(p) != RTLIL::State::Sm)
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p--, offset++;
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RTLIL::SigSpec sig_a;
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for (p++; driven_bits.at(p) != RTLIL::State::Sm; p++)
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sig_a.append(driven_bits.at(p));
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RTLIL::SigSpec new_sig = sig;
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if (sig_a.size() != sig.size()) {
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RTLIL::Cell *cell = module->addCell(NEW_ID, "$slice");
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cell->parameters["\\OFFSET"] = offset;
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cell->parameters["\\A_WIDTH"] = sig_a.size();
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cell->parameters["\\Y_WIDTH"] = sig.size();
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cell->setPort("\\A", sig_a);
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cell->setPort("\\Y", module->addWire(NEW_ID, sig.size()));
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new_sig = cell->getPort("\\Y");
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}
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sliced_signals_cache[sig] = new_sig;
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return new_sig;
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}
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RTLIL::SigSpec get_spliced_signal(RTLIL::SigSpec sig)
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{
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if (sig.size() == 0 || sig.is_fully_const())
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return sig;
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if (spliced_signals_cache.count(sig))
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return spliced_signals_cache.at(sig);
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int last_bit = -1;
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std::vector<RTLIL::SigSpec> chunks;
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for (auto &bit : sig.to_sigbit_vector())
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{
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if (bit.wire == NULL)
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{
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if (last_bit == 0)
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chunks.back().append(bit);
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else
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chunks.push_back(bit);
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last_bit = 0;
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continue;
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}
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if (driven_bits_map.count(bit))
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{
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int this_bit = driven_bits_map.at(bit);
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if (last_bit+1 == this_bit)
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chunks.back().append(bit);
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else
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chunks.push_back(bit);
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last_bit = this_bit;
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continue;
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}
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log(" Failed to generate spliced signal %s.\n", log_signal(sig));
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spliced_signals_cache[sig] = sig;
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return sig;
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}
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RTLIL::SigSpec new_sig = get_sliced_signal(chunks.front());
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for (size_t i = 1; i < chunks.size(); i++) {
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RTLIL::SigSpec sig2 = get_sliced_signal(chunks[i]);
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RTLIL::Cell *cell = module->addCell(NEW_ID, "$concat");
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cell->parameters["\\A_WIDTH"] = new_sig.size();
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cell->parameters["\\B_WIDTH"] = sig2.size();
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cell->setPort("\\A", new_sig);
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cell->setPort("\\B", sig2);
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cell->setPort("\\Y", module->addWire(NEW_ID, new_sig.size() + sig2.size()));
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new_sig = cell->getPort("\\Y");
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}
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spliced_signals_cache[sig] = new_sig;
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log(" Created spliced signal: %s -> %s\n", log_signal(sig), log_signal(new_sig));
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return new_sig;
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}
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void run()
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{
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log("Splicing signals in module %s:\n", RTLIL::id2cstr(module->name));
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driven_bits.push_back(RTLIL::State::Sm);
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driven_bits.push_back(RTLIL::State::Sm);
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for (auto &it : module->wires_)
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if (it.second->port_input) {
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RTLIL::SigSpec sig = sigmap(it.second);
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driven_chunks.insert(sig);
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for (auto &bit : sig.to_sigbit_vector())
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driven_bits.push_back(bit);
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driven_bits.push_back(RTLIL::State::Sm);
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}
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for (auto &it : module->cells_)
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for (auto &conn : it.second->connections())
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if (!ct.cell_known(it.second->type) || ct.cell_output(it.second->type, conn.first)) {
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RTLIL::SigSpec sig = sigmap(conn.second);
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driven_chunks.insert(sig);
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for (auto &bit : sig.to_sigbit_vector())
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driven_bits.push_back(bit);
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driven_bits.push_back(RTLIL::State::Sm);
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}
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driven_bits.push_back(RTLIL::State::Sm);
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for (size_t i = 0; i < driven_bits.size(); i++)
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driven_bits_map[driven_bits[i]] = i;
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SigPool selected_bits;
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if (!sel_by_cell)
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for (auto &it : module->wires_)
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if (design->selected(module, it.second))
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selected_bits.add(sigmap(it.second));
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for (auto &it : module->cells_) {
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if (!sel_by_wire && !design->selected(module, it.second))
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continue;
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for (auto &conn : it.second->connections_)
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if (ct.cell_input(it.second->type, conn.first)) {
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if (ports.size() > 0 && !ports.count(conn.first))
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continue;
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if (no_ports.size() > 0 && no_ports.count(conn.first))
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continue;
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RTLIL::SigSpec sig = sigmap(conn.second);
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if (!sel_by_cell) {
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if (!sel_any_bit && !selected_bits.check_all(sig))
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continue;
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if (sel_any_bit && !selected_bits.check_any(sig))
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continue;
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}
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if (driven_chunks.count(sig) > 0)
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continue;
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conn.second = get_spliced_signal(sig);
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}
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}
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std::vector<std::pair<RTLIL::Wire*, RTLIL::SigSpec>> rework_wires;
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for (auto &it : module->wires_)
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if (!no_outputs && it.second->port_output) {
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if (!design->selected(module, it.second))
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continue;
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RTLIL::SigSpec sig = sigmap(it.second);
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if (driven_chunks.count(sig) > 0)
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continue;
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RTLIL::SigSpec new_sig = get_spliced_signal(sig);
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if (new_sig != sig)
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rework_wires.push_back(std::pair<RTLIL::Wire*, RTLIL::SigSpec>(it.second, new_sig));
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} else
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if (!it.second->port_input) {
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RTLIL::SigSpec sig = sigmap(it.second);
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if (spliced_signals_cache.count(sig) && spliced_signals_cache.at(sig) != sig)
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rework_wires.push_back(std::pair<RTLIL::Wire*, RTLIL::SigSpec>(it.second, spliced_signals_cache.at(sig)));
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else if (sliced_signals_cache.count(sig) && sliced_signals_cache.at(sig) != sig)
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rework_wires.push_back(std::pair<RTLIL::Wire*, RTLIL::SigSpec>(it.second, sliced_signals_cache.at(sig)));
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}
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for (auto &it : rework_wires)
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{
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RTLIL::IdString orig_name = it.first->name;
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module->rename(it.first, NEW_ID);
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RTLIL::Wire *new_port = module->addWire(orig_name, it.first);
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it.first->port_id = 0;
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it.first->port_input = false;
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it.first->port_output = false;
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module->connect(RTLIL::SigSig(new_port, it.second));
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}
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}
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};
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struct SplicePass : public Pass {
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SplicePass() : Pass("splice", "create explicit splicing cells") { }
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virtual void help()
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" splice [options] [selection]\n");
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log("\n");
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log("This command adds $slice and $concat cells to the design to make the splicing\n");
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log("of multi-bit signals explicit. This for example is useful for coarse grain\n");
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log("synthesis, where dedidacted hardware is needed to splice signals.\n");
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log("\n");
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log(" -sel_by_cell\n");
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log(" only select the cell ports to rewire by the cell. if the selection\n");
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log(" contains a cell, than all cell inputs are rewired, if necessary.\n");
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log("\n");
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log(" -sel_by_wire\n");
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log(" only select the cell ports to rewire by the wire. if the selection\n");
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log(" contains a wire, than all cell ports driven by this wire are wired,\n");
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log(" if necessary.\n");
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log("\n");
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log(" -sel_any_bit\n");
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log(" it is sufficient if the driver of any bit of a cell port is selected.\n");
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log(" by default all bits must be selected.\n");
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log("\n");
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log(" -no_outputs\n");
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log(" do not rewire selected module outputs.\n");
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log("\n");
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log(" -port <name>\n");
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log(" only rewire cell ports with the specified name. can be used multiple\n");
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log(" times. implies -no_output.\n");
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log("\n");
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log(" -no_port <name>\n");
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log(" do not rewire cell ports with the specified name. can be used multiple\n");
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log(" times. can not be combined with -port <name>.\n");
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log("\n");
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log("By default selected output wires and all cell ports of selected cells driven\n");
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log("by selected wires are rewired.\n");
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log("\n");
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}
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virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
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{
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bool sel_by_cell = false;
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bool sel_by_wire = false;
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bool sel_any_bit = false;
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bool no_outputs = false;
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std::set<RTLIL::IdString> ports, no_ports;
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++) {
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if (args[argidx] == "-sel_by_cell") {
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sel_by_cell = true;
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continue;
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}
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if (args[argidx] == "-sel_by_wire") {
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sel_by_wire = true;
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continue;
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}
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if (args[argidx] == "-sel_any_bit") {
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sel_any_bit = true;
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continue;
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}
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if (args[argidx] == "-no_outputs") {
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no_outputs = true;
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continue;
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}
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if (args[argidx] == "-port" && argidx+1 < args.size()) {
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ports.insert(RTLIL::escape_id(args[++argidx]));
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no_outputs = true;
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continue;
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}
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if (args[argidx] == "-no_port" && argidx+1 < args.size()) {
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no_ports.insert(RTLIL::escape_id(args[++argidx]));
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continue;
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}
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break;
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}
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extra_args(args, argidx, design);
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if (sel_by_cell && sel_by_wire)
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log_cmd_error("The options -sel_by_cell and -sel_by_wire are exclusive!\n");
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if (sel_by_cell && sel_any_bit)
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log_cmd_error("The options -sel_by_cell and -sel_any_bit are exclusive!\n");
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if (!ports.empty() && !no_ports.empty())
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log_cmd_error("The options -port and -no_port are exclusive!\n");
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log_header("Executing SPLICE pass (creating cells for signal splicing).\n");
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for (auto &mod_it : design->modules_)
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{
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if (!design->selected(mod_it.second))
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continue;
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if (mod_it.second->processes.size()) {
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log("Skipping module %s as it contains processes.\n", mod_it.second->name.c_str());
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continue;
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}
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SpliceWorker worker(design, mod_it.second);
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worker.sel_by_cell = sel_by_cell;
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worker.sel_by_wire = sel_by_wire;
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worker.sel_any_bit = sel_any_bit;
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worker.no_outputs = no_outputs;
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worker.ports = ports;
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worker.no_ports = no_ports;
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worker.run();
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}
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}
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} SplicePass;
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